1/* 2 * Broadcom SiliconBackplane SDIO/PCMCIA hardware-specific 3 * device core support 4 * 5 * Copyright 2007, Broadcom Corporation 6 * All Rights Reserved. 7 * 8 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY 9 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM 10 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS 11 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. 12 * 13 * $Id: sbsdpcmdev.h,v 1.1.1.1 2008/10/15 03:25:54 james26_jang Exp $ 14 */ 15 16#ifndef _sbsdpcmdev_h_ 17#define _sbsdpcmdev_h_ 18 19/* cpp contortions to concatenate w/arg prescan */ 20#ifndef PAD 21#define _PADLINE(line) pad ## line 22#define _XSTR(line) _PADLINE(line) 23#define PAD _XSTR(__LINE__) 24#endif /* PAD */ 25 26 27/* core registers */ 28typedef volatile struct { 29 uint32 corecontrol; /* CoreControl, 0x000, rev8 */ 30 uint32 corestatus; /* CoreStatus, 0x004, rev8 */ 31 uint32 PAD[1]; 32 uint32 biststatus; /* BistStatus, 0x00c, rev8 */ 33 34 /* PCMCIA access */ 35 uint16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */ 36 uint16 PAD[1]; 37 uint16 pcmciamesportalmask; /* PcmciaMesPortalMask, 0x014, rev8 */ 38 uint16 PAD[1]; 39 uint16 pcmciawrframebc; /* PcmciaWrFrameBC, 0x018, rev8 */ 40 uint16 PAD[1]; 41 uint16 pcmciaunderflowtimer; /* PcmciaUnderflowTimer, 0x01c, rev8 */ 42 uint16 PAD[1]; 43 44 /* interrupt */ 45 uint32 intstatus; /* IntStatus, 0x020, rev8 */ 46 uint32 hostintmask; /* IntHostMask, 0x024, rev8 */ 47 uint32 intmask; /* IntSbMask, 0x028, rev8 */ 48 uint32 sbintstatus; /* SBIntStatus, 0x02c, rev8 */ 49 uint32 sbintmask; /* SBIntMask, 0x030, rev8 */ 50 uint32 PAD[3]; 51 uint32 tosbmailbox; /* ToSBMailbox, 0x040, rev8 */ 52 uint32 tohostmailbox; /* ToHostMailbox, 0x044, rev8 */ 53 uint32 tosbmailboxdata; /* ToSbMailboxData, 0x048, rev8 */ 54 uint32 tohostmailboxdata; /* ToHostMailboxData, 0x04c, rev8 */ 55 56 57 /* synchronized access to registers in SDIO clock domain */ 58 uint32 sdioaccess; /* SdioAccess, 0x050, rev8 */ 59 uint32 PAD[3]; 60 61 /* PCMCIA frame control */ 62 uint8 pcmciaframectrl; /* pcmciaFrameCtrl, 0x060, rev8 */ 63 uint8 PAD[3]; 64 uint8 pcmciawatermark; /* pcmciaWaterMark, 0x064, rev8 */ 65 uint8 PAD[155]; 66 67 /* interrupt batching control */ 68 uint32 intrcvlazy; /* IntRcvLazy, 0x100, rev8 */ 69 uint32 PAD[3]; 70 71 /* counters */ 72 uint32 cmd52rd; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */ 73 uint32 cmd52wr; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */ 74 uint32 cmd53rd; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */ 75 uint32 cmd53wr; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */ 76 uint32 abort; /* AbortCount, 0x120, rev8, SDIO: aborts */ 77 uint32 datacrcerror; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */ 78 uint32 rdoutofsync; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */ 79 uint32 wroutofsync; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */ 80 uint32 writebusy; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */ 81 uint32 readwait; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */ 82 uint32 readterm; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */ 83 uint32 writeterm; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */ 84 uint32 PAD[40]; 85 uint32 clockctlstatus; /* ClockCtlStatus, 0x1e0, rev8 */ 86 uint32 PAD[7]; 87 88 /* DMA engines */ 89 dma32regp_t dmaregs; /* DMA Regs, 0x200-0x21c, rev8 */ 90 dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x220-0x22c */ 91 uint32 PAD[116]; 92 93 /* SDIO/PCMCIA CIS region */ 94 char cis[512]; /* 512 byte CIS, 0x400-0x5ff, rev6 */ 95 96 /* PCMCIA function control registers */ 97 char pcmciafcr[256]; /* PCMCIA FCR, 0x600-6ff, rev6 */ 98 uint16 PAD[55]; 99 100 /* PCMCIA backplane access */ 101 uint16 backplanecsr; /* BackplaneCSR, 0x76E, rev6 */ 102 uint16 backplaneaddr0; /* BackplaneAddr0, 0x770, rev6 */ 103 uint16 backplaneaddr1; /* BackplaneAddr1, 0x772, rev6 */ 104 uint16 backplaneaddr2; /* BackplaneAddr2, 0x774, rev6 */ 105 uint16 backplaneaddr3; /* BackplaneAddr3, 0x776, rev6 */ 106 uint16 backplanedata0; /* BackplaneData0, 0x778, rev6 */ 107 uint16 backplanedata1; /* BackplaneData1, 0x77a, rev6 */ 108 uint16 backplanedata2; /* BackplaneData2, 0x77c, rev6 */ 109 uint16 backplanedata3; /* BackplaneData3, 0x77e, rev6 */ 110 uint16 PAD[31]; 111 112 /* sprom "size" & "blank" info */ 113 uint16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */ 114 uint32 PAD[464]; 115 116 /* Sonics SiliconBackplane registers */ 117 sbconfig_t sbconfig; /* SbConfig Regs, 0xf00-0xfff, rev8 */ 118} sdpcmd_regs_t; 119 120/* corecontrol */ 121#define CC_CISRDY (1L << 0) /* CIS Ready */ 122#define CC_BPRESEN (1L << 1) /* CCCR RES signal causes backplane reset */ 123#define CC_F2RDY (1L << 2) /* set CCCR IOR2 bit */ 124 125/* corestatus */ 126#define CS_PCMCIAMODE (1L << 0) /* Device Mode; 0=SDIO, 1=PCMCIA */ 127#define CS_SMARTDEV (1L << 1) /* 1=smartDev enabled */ 128#define CS_F2ENABLED (1L << 2) /* 1=host has enabled the device */ 129 130#define PCMCIA_MES_PA_MASK 0x7fff /* PCMCIA Message Portal Address Mask */ 131#define PCMCIA_MES_PM_MASK 0x7fff /* PCMCIA Message Portal Mask Mask */ 132#define PCMCIA_WFBC_MASK 0xffff /* PCMCIA Write Frame Byte Count Mask */ 133#define PCMCIA_UT_MASK 0x07ff /* PCMCIA Underflow Timer Mask */ 134 135/* intstatus - hw defs */ 136#define I_WR_OOSYNC (1L << 8) /* Write Frame Out Of Sync */ 137#define I_RD_OOSYNC (1L << 9) /* Read Frame Out Of Sync */ 138#define I_PC (1L << 10) /* descriptor error */ 139#define I_PD (1L << 11) /* data error */ 140#define I_DE (1L << 12) /* Descriptor protocol Error */ 141#define I_RU (1L << 13) /* Receive descriptor Underflow */ 142#define I_RO (1L << 14) /* Receive fifo Overflow */ 143#define I_XU (1L << 15) /* Transmit fifo Underflow */ 144#define I_RI (1L << 16) /* Receive Interrupt */ 145#define I_BUSPWR (1L << 17) /* SDIO Bus Power Change (rev 9) */ 146#define I_XI (1L << 24) /* Transmit Interrupt */ 147#define I_RF_TERM (1L << 25) /* Read Frame Terminate */ 148#define I_WF_TERM (1L << 26) /* Write Frame Terminate */ 149#define I_PCMCIA_XU (1L << 27) /* PCMCIA Transmit FIFO Underflow */ 150#define I_SBINT (1L << 28) /* sbintstatus Interrupt */ 151#define I_CHIPACTIVE (1L << 29) /* chip transitioned from doze to active state */ 152#define I_SRESET (1L << 30) /* CCCR RES interrupt */ 153#define I_IOE2 (1L << 31) /* CCCR IOE2 Bit Changed */ 154#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) /* DMA Errors */ 155#define I_DMA (I_RI | I_XI | I_ERRORS) 156/* ToSbMailbox and ToHostMailbox Ints */ 157#define I_TOSBMAIL (I_SMB_NAK | I_SMB_INT_ACK | I_SMB_USE_OOB | I_SMB_DEV_INT) 158#define I_TOHOSTMAIL (I_HMB_FC_CHANGE | I_HMB_FRAME_IND | I_HMB_HOST_INT) /* ToHostMailbox */ 159 160/* sbintstatus */ 161#define I_SB_SERR (1 << 8) /* Backplane SError (write) */ 162#define I_SB_RESPERR (1 << 9) /* Backplane Response Error (read) */ 163#define I_SB_SPROMERR (1 << 10) /* Error accessing the sprom */ 164 165/* sdioaccess */ 166#define SDA_DATA_MASK 0x000000ff /* Read/Write Data Mask */ 167#define SDA_ADDR_MASK 0x000fff00 /* Read/Write Address Mask */ 168#define SDA_ADDR_SHIFT 8 /* Read/Write Address Shift */ 169#define SDA_WRITE 0x01000000 /* Write bit */ 170#define SDA_READ 0x00000000 /* Write bit cleared for Read */ 171#define SDA_BUSY 0x80000000 /* Busy bit */ 172 173/* sdioaccess-accessible register address spaces */ 174#define SDA_CCCR_SPACE 0x000 /* sdioAccess CCCR register space */ 175#define SDA_F1_FBR_SPACE 0x100 /* sdioAccess F1 FBR register space */ 176#define SDA_F2_FBR_SPACE 0x200 /* sdioAccess F2 FBR register space */ 177#define SDA_F1_REG_SPACE 0x300 /* sdioAccess F1 core-specific register space */ 178 179/* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */ 180#define SDA_CHIPCONTROLDATA 0x006 /* ChipControlData */ 181#define SDA_CHIPCONTROLENAB 0x007 /* ChipControlEnable */ 182#define SDA_F2WATERMARK 0x008 /* Function 2 Watermark */ 183#define SDA_DEVICECONTROL 0x009 /* DeviceControl */ 184#define SDA_SBADDRLOW 0x00a /* SbAddrLow */ 185#define SDA_SBADDRMID 0x00b /* SbAddrMid */ 186#define SDA_SBADDRHIGH 0x00c /* SbAddrHigh */ 187#define SDA_FRAMECTRL 0x00d /* FrameCtrl */ 188#define SDA_CHIPCLOCKCSR 0x00e /* ChipClockCSR */ 189#define SDA_SDIOPULLUP 0x00f /* SdioPullUp */ 190#define SDA_SDIOWRFRAMEBCLOW 0x019 /* SdioWrFrameBCLow */ 191#define SDA_SDIOWRFRAMEBCHIGH 0x01a /* SdioWrFrameBCHigh */ 192#define SDA_SDIORDFRAMEBCLOW 0x01b /* SdioRdFrameBCLow */ 193#define SDA_SDIORDFRAMEBCHIGH 0x01c /* SdioRdFrameBCHigh */ 194 195/* SDA_F2WATERMARK */ 196#define SDA_F2WATERMARK_MASK 0x7f /* F2Watermark Mask */ 197 198/* SDA_SBADDRLOW */ 199#define SDA_SBADDRLOW_MASK 0x80 /* SbAddrLow Mask */ 200 201/* SDA_SBADDRMID */ 202#define SDA_SBADDRMID_MASK 0xff /* SbAddrMid Mask */ 203 204/* SDA_SBADDRHIGH */ 205#define SDA_SBADDRHIGH_MASK 0xff /* SbAddrHigh Mask */ 206 207/* SDA_FRAMECTRL */ 208#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ 209#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ 210#define SFC_CRC4WOOS (1 << 2) /* HW reports CRC error for write out of sync */ 211#define SFC_ABORTALL (1 << 3) /* Abort cancels all in-progress frames */ 212 213/* pcmciaframectrl */ 214#define PFC_RF_TERM (1 << 0) /* Read Frame Terminate */ 215#define PFC_WF_TERM (1 << 1) /* Write Frame Terminate */ 216 217/* intrcvlazy */ 218#define IRL_TO_MASK 0x00ffffff /* timeout */ 219#define IRL_FC_MASK 0xff000000 /* frame count */ 220#define IRL_FC_SHIFT 24 /* frame count */ 221 222/* rx header */ 223typedef volatile struct { 224 uint16 len; 225 uint16 flags; 226} sdpcmd_rxh_t; 227 228/* rx header flags */ 229#define RXF_CRC 0x0001 /* CRC error detected */ 230#define RXF_WOOS 0x0002 /* write frame out of sync */ 231#define RXF_WF_TERM 0x0004 /* write frame terminated */ 232#define RXF_ABORT 0x0008 /* write frame aborted */ 233#define RXF_DISCARD (RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT) /* bad frame */ 234 235/* HW frame tag */ 236#define SDPCM_FRAMETAG_LEN 4 /* HW frametag: 2 bytes len, 2 bytes check val */ 237 238/* 239 * ******************************************************************* 240 * SOFTWARE DEFINITIONS 241 * ******************************************************************* 242 */ 243 244/* intstatus register - sw defs */ 245#define I_SMB_NAK (1L << 0) /* To SB Mailbox Frame NAK */ 246#define I_SMB_INT_ACK (1L << 1) /* To SB Mailbox Host Interrupt ACK */ 247#define I_SMB_USE_OOB (1L << 2) /* To SB Mailbox Use OOB Wakeup */ 248#define I_SMB_DEV_INT (1L << 3) /* To SB Mailbox Miscellaneous Interrupt */ 249#define I_HMB_FC_STATE (1L << 4) /* To Host Mailbox Flow Control State */ 250#define I_HMB_FC_CHANGE (1L << 5) /* To Host Mailbox Flow Control State Changed */ 251#define I_HMB_FRAME_IND (1L << 6) /* To Host Mailbox Frame Indication */ 252#define I_HMB_HOST_INT (1L << 7) /* To Host Mailbox Miscellaneous Interrupt */ 253 254/* intstatus register masks for sw mailbox interrupts */ 255#define SMB_MASK 0x0000000f /* ToSBMailbox Mask */ 256#define HMB_MASK 0x000000f0 /* ToHostMailbox Mask */ 257#define HMB_SHIFT 4 /* ToHostMailbox Shift */ 258 259/* tosbmailbox & tohostmailbox - sw defs */ 260#define MB_MASK 0x0000000f /* ToSBMailbox & ToHostMailbox Mask */ 261#define SMB_NAK (1L << 0) /* To SB Mailbox Frame NAK */ 262#define SMB_INT_ACK (1L << 1) /* To SB Mailbox Host Interrupt ACK */ 263#define SMB_USE_OOB (1L << 2) /* To SB Mailbox Use OOB Wakeup */ 264#define SMB_DEV_INT (1L << 3) /* To SB Mailbox Miscellaneous Interrupt */ 265#define HMB_FC_ON (1L << 0) /* To Host Mailbox Flow Control State=ON */ 266#define HMB_FC_CHANGE (1L << 1) /* To Host Mailbox Flow Control State Changed */ 267#define HMB_FRAME_IND (1L << 2) /* To Host Mailbox Frame Indication */ 268#define HMB_HOST_INT (1L << 3) /* To Host Mailbox Miscellaneous Interrupt */ 269 270/* tohostmailboxdata - sw defs */ 271#define HMB_DATA_NAKHANDLED 1 /* we're ready to retransmit NAK'd frame to host */ 272#define HMB_DATA_DEVREADY 2 /* we're ready to to talk to host after enable */ 273#define HMB_DATA_FC 4 /* per prio flowcontrol update flag to host */ 274 275#define HMB_DATA_FCDATA_MASK 0xff /* per prio flowcontrol data */ 276#define HMB_DATA_FCDATA_SHIFT 24 /* per prio flowcontrol data */ 277 278/* SW frame header */ 279#define SDPCM_SEQUENCE_MASK 0x000000ff /* Sequence Number Mask */ 280#define SDPCM_PACKET_SEQUENCE(p) (((uint8 *)p)[0] & 0xff) /* p starts w/SW Header */ 281#define SDPCM_CHANNEL_MASK 0x00000f00 /* Channel Number Mask */ 282#define SDPCM_CHANNEL_SHIFT 8 /* Channel Number Shift */ 283#define SDPCM_PACKET_CHANNEL(p) (((uint8 *)p)[1] & 0x0f) /* p starts w/SW Header */ 284#define SDPCM_PRIORITY_MASK 0x0000f000 /* Pkt Priority Value Mask */ 285#define SDPCM_PRIORITY_SHIFT 12 /* Pkt Priority Value Shift */ 286#define SDPCM_PACKET_PRIORITY(p) ((((uint8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */ 287 288#define SDPCM_SWHEADER_LEN 4 /* SW header is 32 bits */ 289 290/* logical channel numbers */ 291#define SDPCM_CONTROL_CHANNEL 0 /* Control Request/Response Channel Id */ 292#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */ 293#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */ 294#define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */ 295 296#define SDPCM_MAX_SEQUENCE 256 /* wrap-around val for eight-bit frame seq number */ 297 298/* For TEST_CHANNEL packets, define another 4-byte header */ 299#define SDPCM_TEST_HDRLEN 4 /* Generally: Cmd(1), Ext(1), Len(2); 300 * Semantics of Ext byte depend on command. 301 * Len is current or requested frame length, not 302 * including test header; sent little-endian. 303 */ 304#define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext is a pattern id. */ 305#define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext is a pattern id. */ 306#define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext is a pattern id. */ 307#define SDPCM_TEST_BURST 0x04 /* Receiver to send a burst. Ext is a frame count */ 308#define SDPCM_TEST_SEND 0x05 /* Receiver sets send mode. Ext is boolean on/off */ 309 310/* Handy macro for filling in datagen packets with a pattern */ 311#define SDPCM_TEST_FILL(byteno, id) ((uint8)(id + byteno)) 312 313 314/* software copy of hardware counters */ 315typedef volatile struct { 316 uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */ 317 uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */ 318 uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */ 319 uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */ 320 uint32 abort; /* AbortCount, SDIO: aborts */ 321 uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */ 322 uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */ 323 uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */ 324 uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */ 325 uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */ 326 uint32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */ 327 uint32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */ 328 uint32 rxdescuflo; /* receive descriptor underflows */ 329 uint32 rxfifooflo; /* receive fifo overflows */ 330 uint32 txfifouflo; /* transmit fifo underflows */ 331 uint32 runt; /* runt (too short) frames recv'd from bus */ 332 uint32 badlen; /* frame's rxh len does not match its hw tag len */ 333 uint32 badcksum; /* frame's hw tag chksum doesn't agree with len value */ 334 uint32 seqbreak; /* break in sequence # space from one rx frame to the next */ 335 uint32 rxfcrc; /* frame rx header indicates crc error */ 336 uint32 rxfwoos; /* frame rx header indicates write out of sync */ 337 uint32 rxfwft; /* frame rx header indicates write frame termination */ 338 uint32 rxfabort; /* frame rx header indicates frame aborted */ 339 uint32 woosint; /* write out of sync interrupt */ 340 uint32 roosint; /* read out of sync interrupt */ 341 uint32 rftermint; /* read frame terminate interrupt */ 342 uint32 wftermint; /* write frame terminate interrupt */ 343} sdpcmd_cnt_t; 344 345#endif /* _sbsdpcmdev_h_ */ 346