1/* 2 * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions. 3 * 4 * Copyright 2007, Broadcom Corporation 5 * All Rights Reserved. 6 * 7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY 8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM 9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS 10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. 11 * 12 * $Id: sbpcmcia.h,v 1.1.1.1 2008/10/15 03:25:54 james26_jang Exp $ 13 */ 14 15#ifndef _SBPCMCIA_H 16#define _SBPCMCIA_H 17 18 19/* All the addresses that are offsets in attribute space are divided 20 * by two to account for the fact that odd bytes are invalid in 21 * attribute space and our read/write routines make the space appear 22 * as if they didn't exist. Still we want to show the original numbers 23 * as documented in the hnd_pcmcia core manual. 24 */ 25 26/* PCMCIA Function Configuration Registers */ 27#define PCMCIA_FCR (0x700 / 2) 28 29#define FCR0_OFF 0 30#define FCR1_OFF (0x40 / 2) 31#define FCR2_OFF (0x80 / 2) 32#define FCR3_OFF (0xc0 / 2) 33 34#define PCMCIA_FCR0 (0x700 / 2) 35#define PCMCIA_FCR1 (0x740 / 2) 36#define PCMCIA_FCR2 (0x780 / 2) 37#define PCMCIA_FCR3 (0x7c0 / 2) 38 39/* Standard PCMCIA FCR registers */ 40 41#define PCMCIA_COR 0 42 43#define COR_RST 0x80 44#define COR_LEV 0x40 45#define COR_IRQEN 0x04 46#define COR_BLREN 0x01 47#define COR_FUNEN 0x01 48 49 50#define PCICIA_FCSR (2 / 2) 51#define PCICIA_PRR (4 / 2) 52#define PCICIA_SCR (6 / 2) 53#define PCICIA_ESR (8 / 2) 54 55 56#define PCM_MEMOFF 0x0000 57#define F0_MEMOFF 0x1000 58#define F1_MEMOFF 0x2000 59#define F2_MEMOFF 0x3000 60#define F3_MEMOFF 0x4000 61 62/* Memory base in the function fcr's */ 63#define MEM_ADDR0 (0x728 / 2) 64#define MEM_ADDR1 (0x72a / 2) 65#define MEM_ADDR2 (0x72c / 2) 66 67/* PCMCIA base plus Srom access in fcr0: */ 68#define PCMCIA_ADDR0 (0x072e / 2) 69#define PCMCIA_ADDR1 (0x0730 / 2) 70#define PCMCIA_ADDR2 (0x0732 / 2) 71 72#define MEM_SEG (0x0734 / 2) 73#define SROM_CS (0x0736 / 2) 74#define SROM_DATAL (0x0738 / 2) 75#define SROM_DATAH (0x073a / 2) 76#define SROM_ADDRL (0x073c / 2) 77#define SROM_ADDRH (0x073e / 2) 78#define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */ 79#define SROM_INFO (0x07be / 2) /* Corerev >= 6 */ 80 81/* Values for srom_cs: */ 82#define SROM_IDLE 0 83#define SROM_WRITE 1 84#define SROM_READ 2 85#define SROM_WEN 4 86#define SROM_WDS 7 87#define SROM_DONE 8 88 89/* Fields in srom_info: */ 90#define SRI_SZ_MASK 0x03 91#define SRI_BLANK 0x04 92#define SRI_OTP 0x80 93 94/* CIS stuff */ 95 96/* The CIS stops where the FCRs start */ 97#define CIS_SIZE PCMCIA_FCR 98 99/* CIS tuple length field max */ 100#define CIS_TUPLE_LEN_MAX 0xff 101 102/* Standard tuples we know about */ 103 104#define CISTPL_VERS_1 0x15 /* CIS ver, manf, dev & ver strings */ 105#define CISTPL_MANFID 0x20 /* Manufacturer and device id */ 106#define CISTPL_FUNCID 0x21 /* Function identification */ 107#define CISTPL_FUNCE 0x22 /* Function extensions */ 108#define CISTPL_CFTABLE 0x1b /* Config table entry */ 109#define CISTPL_END 0xff /* End of the CIS tuple chain */ 110 111/* Function identifier provides context for the function extentions tuple */ 112 113 114/* Function extensions for LANs */ 115 116#define LAN_TECH 1 /* Technology type */ 117#define LAN_SPEED 2 /* Raw bit rate */ 118#define LAN_MEDIA 3 /* Transmission media */ 119#define LAN_NID 4 /* Node identification (aka MAC addr) */ 120#define LAN_CONN 5 /* Connector standard */ 121 122 123/* CFTable */ 124#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */ 125#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */ 126#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */ 127 128/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll 129 * take one for HNBU, and use "extensions" (a la FUNCE) within it. 130 */ 131 132#define CISTPL_BRCM_HNBU 0x80 133 134/* Subtypes of BRCM_HNBU: */ 135 136#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */ 137#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */ 138#define HNBU_BOARDREV 0x02 /* One byte board revision */ 139#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1) 140 * or 9 (sromrev > 1) bytes 141 */ 142#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */ 143#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */ 144#define HNBU_AA 0x06 /* Antennas available */ 145#define HNBU_AG 0x07 /* Antenna gain */ 146#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */ 147#define HNBU_LEDS 0x09 /* LED set */ 148#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl) 149 * in rev 2 150 */ 151#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */ 152#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */ 153#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */ 154#define HNBU_PAPARMS5G 0x0e /* 5G PA params */ 155#define HNBU_ANT5G 0x0f /* 4328 5G antennas available/gain */ 156#define HNBU_RDLID 0x10 /* 2 byte USB remote downloader (RDL) product Id */ 157#define HNBU_RSSISMBXA2G 0x11 /* 4328 2G RSSI mid pt sel & board switch arch, 158 * 2 bytes, rev 3. 159 */ 160#define HNBU_RSSISMBXA5G 0x12 /* 4328 5G RSSI mid pt sel & board switch arch, 161 * 2 bytes, rev 3. 162 */ 163#define HNBU_XTALFREQ 0x13 /* 4 byte Crystal frequency in kilohertz */ 164#define HNBU_TRI2G 0x14 /* 4328 2G TR isolation, 1 byte */ 165#define HNBU_TRI5G 0x15 /* 4328 5G TR isolation, 3 bytes */ 166#define HNBU_RXPO2G 0x16 /* 4328 2G RX power offset, 1 byte */ 167#define HNBU_RXPO5G 0x17 /* 4328 5G RX power offset, 1 byte */ 168#define HNBU_BOARDNUM 0x18 /* board serial number, independent of mac addr */ 169#define HNBU_MACADDR 0x19 /* mac addr override for the standard CIS LAN_NID */ 170#define HNBU_RDLSN 0x1a /* 2 bytes; serial # advertised in USB descriptor */ 171#define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */ 172#define HNBU_RDLRNDIS 0x20 /* 1 byte; 1 = RDL advertises RNDIS config */ 173#define HNBU_RDLRWU 0x30 /* 1 byte; 1 = RDL advertises Remote Wake-up */ 174#define HNBU_SROM3SWRGN 0x80 /* 78 bytes; srom rev 3 s/w region without crc8 175 * plus extra info appended. 176 */ 177 178/* sbtmstatelow */ 179#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */ 180#define SBTML_INT_EN 0x20000 /* enable sb interrupt */ 181 182/* sbtmstatehigh */ 183#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */ 184 185#endif /* _SBPCMCIA_H */ 186