1/* 2 * pcicfg.h: PCI configuration constants and structures. 3 * 4 * Copyright 2007, Broadcom Corporation 5 * All Rights Reserved. 6 * 7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY 8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM 9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS 10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. 11 * 12 * $Id: pcicfg.h,v 1.1.1.1 2008/10/15 03:25:54 james26_jang Exp $ 13 */ 14 15#ifndef _h_pcicfg_ 16#define _h_pcicfg_ 17 18/* The following inside ifndef's so we don't collide with NTDDK.H */ 19#ifndef PCI_MAX_BUS 20#define PCI_MAX_BUS 0x100 21#endif 22#ifndef PCI_MAX_DEVICES 23#define PCI_MAX_DEVICES 0x20 24#endif 25#ifndef PCI_MAX_FUNCTION 26#define PCI_MAX_FUNCTION 0x8 27#endif 28 29#ifndef PCI_INVALID_VENDORID 30#define PCI_INVALID_VENDORID 0xffff 31#endif 32#ifndef PCI_INVALID_DEVICEID 33#define PCI_INVALID_DEVICEID 0xffff 34#endif 35 36 37/* Convert between bus-slot-function-register and config addresses */ 38 39#define PCICFG_BUS_SHIFT 16 /* Bus shift */ 40#define PCICFG_SLOT_SHIFT 11 /* Slot shift */ 41#define PCICFG_FUN_SHIFT 8 /* Function shift */ 42#define PCICFG_OFF_SHIFT 0 /* Register shift */ 43 44#define PCICFG_BUS_MASK 0xff /* Bus mask */ 45#define PCICFG_SLOT_MASK 0x1f /* Slot mask */ 46#define PCICFG_FUN_MASK 7 /* Function mask */ 47#define PCICFG_OFF_MASK 0xff /* Bus mask */ 48 49#define PCI_CONFIG_ADDR(b, s, f, o) \ 50 ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \ 51 | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \ 52 | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \ 53 | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT)) 54 55#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK) 56#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK) 57#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK) 58#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK) 59 60/* PCIE Config space accessing MACROS */ 61 62#define PCIECFG_BUS_SHIFT 24 /* Bus shift */ 63#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */ 64#define PCIECFG_FUN_SHIFT 16 /* Function shift */ 65#define PCIECFG_OFF_SHIFT 0 /* Register shift */ 66 67#define PCIECFG_BUS_MASK 0xff /* Bus mask */ 68#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */ 69#define PCIECFG_FUN_MASK 7 /* Function mask */ 70#define PCIECFG_OFF_MASK 0x3ff /* Register mask */ 71 72#define PCIE_CONFIG_ADDR(b, s, f, o) \ 73 ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \ 74 | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \ 75 | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \ 76 | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT)) 77 78#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK) 79#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK) 80#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK) 81#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK) 82 83/* The actual config space */ 84 85#define PCI_BAR_MAX 6 86 87#define PCI_ROM_BAR 8 88 89#define PCR_RSVDA_MAX 2 90 91/* Bits in PCI bars' flags */ 92 93#define PCIBAR_FLAGS 0xf 94#define PCIBAR_IO 0x1 95#define PCIBAR_MEM1M 0x2 96#define PCIBAR_MEM64 0x4 97#define PCIBAR_PREFETCH 0x8 98#define PCIBAR_MEM32_MASK 0xFFFFFF80 99 100/* pci config status reg has a bit to indicate that capability ptr is present */ 101 102#define PCI_CAPPTR_PRESENT 0x0010 103 104typedef struct _pci_config_regs { 105 unsigned short vendor; 106 unsigned short device; 107 unsigned short command; 108 unsigned short status; 109 unsigned char rev_id; 110 unsigned char prog_if; 111 unsigned char sub_class; 112 unsigned char base_class; 113 unsigned char cache_line_size; 114 unsigned char latency_timer; 115 unsigned char header_type; 116 unsigned char bist; 117 unsigned long base[PCI_BAR_MAX]; 118 unsigned long cardbus_cis; 119 unsigned short subsys_vendor; 120 unsigned short subsys_id; 121 unsigned long baserom; 122 unsigned long rsvd_a[PCR_RSVDA_MAX]; 123 unsigned char int_line; 124 unsigned char int_pin; 125 unsigned char min_gnt; 126 unsigned char max_lat; 127 unsigned char dev_dep[192]; 128} pci_config_regs; 129 130#define SZPCR (sizeof (pci_config_regs)) 131#define MINSZPCR 64 /* offsetof (dev_dep[0] */ 132 133/* A structure for the config registers is nice, but in most 134 * systems the config space is not memory mapped, so we need 135 * filed offsetts. :-( 136 */ 137#define PCI_CFG_VID 0 138#define PCI_CFG_DID 2 139#define PCI_CFG_CMD 4 140#define PCI_CFG_STAT 6 141#define PCI_CFG_REV 8 142#define PCI_CFG_PROGIF 9 143#define PCI_CFG_SUBCL 0xa 144#define PCI_CFG_BASECL 0xb 145#define PCI_CFG_CLSZ 0xc 146#define PCI_CFG_LATTIM 0xd 147#define PCI_CFG_HDR 0xe 148#define PCI_CFG_BIST 0xf 149#define PCI_CFG_BAR0 0x10 150#define PCI_CFG_BAR1 0x14 151#define PCI_CFG_BAR2 0x18 152#define PCI_CFG_BAR3 0x1c 153#define PCI_CFG_BAR4 0x20 154#define PCI_CFG_BAR5 0x24 155#define PCI_CFG_CIS 0x28 156#define PCI_CFG_SVID 0x2c 157#define PCI_CFG_SSID 0x2e 158#define PCI_CFG_ROMBAR 0x30 159#define PCI_CFG_CAPPTR 0x34 160#define PCI_CFG_INT 0x3c 161#define PCI_CFG_PIN 0x3d 162#define PCI_CFG_MINGNT 0x3e 163#define PCI_CFG_MAXLAT 0x3f 164 165#ifdef __NetBSD__ 166#undef PCI_CLASS_DISPLAY 167#undef PCI_CLASS_MEMORY 168#undef PCI_CLASS_BRIDGE 169#undef PCI_CLASS_INPUT 170#undef PCI_CLASS_DOCK 171#endif /* __NetBSD__ */ 172 173#ifdef EFI 174#undef PCI_CLASS_BRIDGE 175#undef PCI_CLASS_OLD 176#undef PCI_CLASS_DISPLAY 177#undef PCI_CLASS_SERIAL 178#undef PCI_CLASS_SATELLITE 179#endif /* EFI */ 180 181/* Classes and subclasses */ 182 183typedef enum { 184 PCI_CLASS_OLD = 0, 185 PCI_CLASS_DASDI, 186 PCI_CLASS_NET, 187 PCI_CLASS_DISPLAY, 188 PCI_CLASS_MMEDIA, 189 PCI_CLASS_MEMORY, 190 PCI_CLASS_BRIDGE, 191 PCI_CLASS_COMM, 192 PCI_CLASS_BASE, 193 PCI_CLASS_INPUT, 194 PCI_CLASS_DOCK, 195 PCI_CLASS_CPU, 196 PCI_CLASS_SERIAL, 197 PCI_CLASS_INTELLIGENT = 0xe, 198 PCI_CLASS_SATELLITE, 199 PCI_CLASS_CRYPT, 200 PCI_CLASS_DSP, 201 PCI_CLASS_XOR = 0xfe 202} pci_classes; 203 204typedef enum { 205 PCI_DASDI_SCSI, 206 PCI_DASDI_IDE, 207 PCI_DASDI_FLOPPY, 208 PCI_DASDI_IPI, 209 PCI_DASDI_RAID, 210 PCI_DASDI_OTHER = 0x80 211} pci_dasdi_subclasses; 212 213typedef enum { 214 PCI_NET_ETHER, 215 PCI_NET_TOKEN, 216 PCI_NET_FDDI, 217 PCI_NET_ATM, 218 PCI_NET_OTHER = 0x80 219} pci_net_subclasses; 220 221typedef enum { 222 PCI_DISPLAY_VGA, 223 PCI_DISPLAY_XGA, 224 PCI_DISPLAY_3D, 225 PCI_DISPLAY_OTHER = 0x80 226} pci_display_subclasses; 227 228typedef enum { 229 PCI_MMEDIA_VIDEO, 230 PCI_MMEDIA_AUDIO, 231 PCI_MMEDIA_PHONE, 232 PCI_MEDIA_OTHER = 0x80 233} pci_mmedia_subclasses; 234 235typedef enum { 236 PCI_MEMORY_RAM, 237 PCI_MEMORY_FLASH, 238 PCI_MEMORY_OTHER = 0x80 239} pci_memory_subclasses; 240 241typedef enum { 242 PCI_BRIDGE_HOST, 243 PCI_BRIDGE_ISA, 244 PCI_BRIDGE_EISA, 245 PCI_BRIDGE_MC, 246 PCI_BRIDGE_PCI, 247 PCI_BRIDGE_PCMCIA, 248 PCI_BRIDGE_NUBUS, 249 PCI_BRIDGE_CARDBUS, 250 PCI_BRIDGE_RACEWAY, 251 PCI_BRIDGE_OTHER = 0x80 252} pci_bridge_subclasses; 253 254typedef enum { 255 PCI_COMM_UART, 256 PCI_COMM_PARALLEL, 257 PCI_COMM_MULTIUART, 258 PCI_COMM_MODEM, 259 PCI_COMM_OTHER = 0x80 260} pci_comm_subclasses; 261 262typedef enum { 263 PCI_BASE_PIC, 264 PCI_BASE_DMA, 265 PCI_BASE_TIMER, 266 PCI_BASE_RTC, 267 PCI_BASE_PCI_HOTPLUG, 268 PCI_BASE_OTHER = 0x80 269} pci_base_subclasses; 270 271typedef enum { 272 PCI_INPUT_KBD, 273 PCI_INPUT_PEN, 274 PCI_INPUT_MOUSE, 275 PCI_INPUT_SCANNER, 276 PCI_INPUT_GAMEPORT, 277 PCI_INPUT_OTHER = 0x80 278} pci_input_subclasses; 279 280typedef enum { 281 PCI_DOCK_GENERIC, 282 PCI_DOCK_OTHER = 0x80 283} pci_dock_subclasses; 284 285typedef enum { 286 PCI_CPU_386, 287 PCI_CPU_486, 288 PCI_CPU_PENTIUM, 289 PCI_CPU_ALPHA = 0x10, 290 PCI_CPU_POWERPC = 0x20, 291 PCI_CPU_MIPS = 0x30, 292 PCI_CPU_COPROC = 0x40, 293 PCI_CPU_OTHER = 0x80 294} pci_cpu_subclasses; 295 296typedef enum { 297 PCI_SERIAL_IEEE1394, 298 PCI_SERIAL_ACCESS, 299 PCI_SERIAL_SSA, 300 PCI_SERIAL_USB, 301 PCI_SERIAL_FIBER, 302 PCI_SERIAL_SMBUS, 303 PCI_SERIAL_OTHER = 0x80 304} pci_serial_subclasses; 305 306typedef enum { 307 PCI_INTELLIGENT_I2O 308} pci_intelligent_subclasses; 309 310typedef enum { 311 PCI_SATELLITE_TV, 312 PCI_SATELLITE_AUDIO, 313 PCI_SATELLITE_VOICE, 314 PCI_SATELLITE_DATA, 315 PCI_SATELLITE_OTHER = 0x80 316} pci_satellite_subclasses; 317 318typedef enum { 319 PCI_CRYPT_NETWORK, 320 PCI_CRYPT_ENTERTAINMENT, 321 PCI_CRYPT_OTHER = 0x80 322} pci_crypt_subclasses; 323 324typedef enum { 325 PCI_DSP_DPIO, 326 PCI_DSP_OTHER = 0x80 327} pci_dsp_subclasses; 328 329typedef enum { 330 PCI_XOR_QDMA, 331 PCI_XOR_OTHER = 0x80 332} pci_xor_subclasses; 333 334/* Header types */ 335typedef enum { 336 PCI_HEADER_NORMAL, 337 PCI_HEADER_BRIDGE, 338 PCI_HEADER_CARDBUS 339} pci_header_types; 340 341 342/* Overlay for a PCI-to-PCI bridge */ 343 344#define PPB_RSVDA_MAX 2 345#define PPB_RSVDD_MAX 8 346 347typedef struct _ppb_config_regs { 348 unsigned short vendor; 349 unsigned short device; 350 unsigned short command; 351 unsigned short status; 352 unsigned char rev_id; 353 unsigned char prog_if; 354 unsigned char sub_class; 355 unsigned char base_class; 356 unsigned char cache_line_size; 357 unsigned char latency_timer; 358 unsigned char header_type; 359 unsigned char bist; 360 unsigned long rsvd_a[PPB_RSVDA_MAX]; 361 unsigned char prim_bus; 362 unsigned char sec_bus; 363 unsigned char sub_bus; 364 unsigned char sec_lat; 365 unsigned char io_base; 366 unsigned char io_lim; 367 unsigned short sec_status; 368 unsigned short mem_base; 369 unsigned short mem_lim; 370 unsigned short pf_mem_base; 371 unsigned short pf_mem_lim; 372 unsigned long pf_mem_base_hi; 373 unsigned long pf_mem_lim_hi; 374 unsigned short io_base_hi; 375 unsigned short io_lim_hi; 376 unsigned short subsys_vendor; 377 unsigned short subsys_id; 378 unsigned long rsvd_b; 379 unsigned char rsvd_c; 380 unsigned char int_pin; 381 unsigned short bridge_ctrl; 382 unsigned char chip_ctrl; 383 unsigned char diag_ctrl; 384 unsigned short arb_ctrl; 385 unsigned long rsvd_d[PPB_RSVDD_MAX]; 386 unsigned char dev_dep[192]; 387} ppb_config_regs; 388 389 390/* PCI CAPABILITY DEFINES */ 391#define PCI_CAP_POWERMGMTCAP_ID 0x01 392#define PCI_CAP_MSICAP_ID 0x05 393#define PCI_CAP_PCIECAP_ID 0x10 394 395/* Data structure to define the Message Signalled Interrupt facility 396 * Valid for PCI and PCIE configurations 397 */ 398typedef struct _pciconfig_cap_msi { 399 unsigned char capID; 400 unsigned char nextptr; 401 unsigned short msgctrl; 402 unsigned int msgaddr; 403} pciconfig_cap_msi; 404 405/* Data structure to define the Power managment facility 406 * Valid for PCI and PCIE configurations 407 */ 408typedef struct _pciconfig_cap_pwrmgmt { 409 unsigned char capID; 410 unsigned char nextptr; 411 unsigned short pme_cap; 412 unsigned short pme_sts_ctrl; 413 unsigned char pme_bridge_ext; 414 unsigned char data; 415} pciconfig_cap_pwrmgmt; 416 417#define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */ 418#define PME_CSR_OFFSET 0x4 /* 4-bytes offset */ 419#define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */ 420#define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */ 421 422/* Data structure to define the PCIE capability */ 423typedef struct _pciconfig_cap_pcie { 424 unsigned char capID; 425 unsigned char nextptr; 426 unsigned short pcie_cap; 427 unsigned int dev_cap; 428 unsigned short dev_ctrl; 429 unsigned short dev_status; 430 unsigned int link_cap; 431 unsigned short link_ctrl; 432 unsigned short link_status; 433} pciconfig_cap_pcie; 434 435/* PCIE Enhanced CAPABILITY DEFINES */ 436#define PCIE_EXTCFG_OFFSET 0x100 437#define PCIE_ADVERRREP_CAPID 0x0001 438#define PCIE_VC_CAPID 0x0002 439#define PCIE_DEVSNUM_CAPID 0x0003 440#define PCIE_PWRBUDGET_CAPID 0x0004 441 442/* Header to define the PCIE specific capabilities in the extended config space */ 443typedef struct _pcie_enhanced_caphdr { 444 unsigned short capID; 445 unsigned short cap_ver : 4; 446 unsigned short next_ptr : 12; 447} pcie_enhanced_caphdr; 448 449 450/* Everything below is BRCM HND proprietary */ 451 452 453/* Brcm PCI configuration registers */ 454#define cap_list rsvd_a[0] 455#define bar0_window dev_dep[0x80 - 0x40] 456#define bar1_window dev_dep[0x84 - 0x40] 457#define sprom_control dev_dep[0x88 - 0x40] 458 459#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */ 460#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */ 461#define PCI_SPROM_CONTROL 0x88 /* sprom property control */ 462#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */ 463#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */ 464#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */ 465#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */ 466#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */ 467#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address */ 468#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */ 469#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */ 470#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */ 471 472#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */ 473#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */ 474#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */ 475#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the 476 * 8KB window, so their address is the "regular" 477 * address plus 4K 478 */ 479#define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */ 480 481/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */ 482#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */ 483#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */ 484#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */ 485 486/* PCI_INT_STATUS */ 487#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */ 488 489/* PCI_INT_MASK */ 490#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */ 491#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */ 492#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */ 493 494/* PCI_SPROM_CONTROL */ 495#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */ 496#define SPROM_LOCKED 0x08 /* SPROM Locked */ 497#define SPROM_BLANK 0x04 /* indicating a blank SPROM */ 498#define SPROM_WRITEEN 0x10 /* SPROM write enable */ 499#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */ 500#define SPROM_OTPIN_USE 0x80 /* device OTP In use */ 501 502#define SPROM_SIZE 256 /* sprom size in 16-bit */ 503#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */ 504 505/* PCI_CFG_CMD_STAT */ 506#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */ 507 508#endif /* _h_pcicfg_ */ 509