1/* 2 * Hardware-specific definitions for 3 * Broadcom BCM47XX 10/100 Mbps Ethernet cores. 4 * 5 * Copyright 2007, Broadcom Corporation 6 * All Rights Reserved. 7 * 8 * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation; 9 * the contents of this file may not be disclosed to third parties, copied 10 * or duplicated in any form, in whole or in part, without the prior 11 * written permission of Broadcom Corporation. 12 * $Id: bcmenet47xx.h,v 1.1.1.1 2008/10/15 03:25:54 james26_jang Exp $ 13 */ 14 15#ifndef _bcmenet_47xx_h_ 16#define _bcmenet_47xx_h_ 17 18#include <bcmenetmib.h> 19#include <bcmenetrxh.h> 20#include <bcmenetphy.h> 21 22#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */ 23#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */ 24#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */ 25#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */ 26 27/* power management event wakeup pattern constants */ 28#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */ 29#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */ 30#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */ 31#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */ 32#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */ 33 34/* cpp contortions to concatenate w/arg prescan */ 35#ifndef PAD 36#define _PADLINE(line) pad ## line 37#define _XSTR(line) _PADLINE(line) 38#define PAD _XSTR(__LINE__) 39#endif /* PAD */ 40 41/* 42 * Host Interface Registers 43 */ 44typedef volatile struct _bcmenettregs { 45 /* Device and Power Control */ 46 uint32 devcontrol; 47 uint32 PAD[2]; 48 uint32 biststatus; 49 uint32 wakeuplength; 50 uint32 PAD[3]; 51 52 /* Interrupt Control */ 53 uint32 intstatus; 54 uint32 intmask; 55 uint32 gptimer; 56 uint32 PAD[23]; 57 58 /* Ethernet MAC Address Filtering Control */ 59 uint32 PAD[2]; 60 uint32 enetftaddr; 61 uint32 enetftdata; 62 uint32 PAD[2]; 63 64 /* Ethernet MAC Control */ 65 uint32 emactxmaxburstlen; 66 uint32 emacrxmaxburstlen; 67 uint32 emaccontrol; 68 uint32 emacflowcontrol; 69 70 uint32 PAD[20]; 71 72 /* DMA Lazy Interrupt Control */ 73 uint32 intrecvlazy; 74 uint32 PAD[63]; 75 76 /* DMA engine */ 77 dma32regp_t dmaregs; 78 dma32diag_t dmafifo; 79 uint32 PAD[116]; 80 81 /* EMAC Registers */ 82 uint32 rxconfig; 83 uint32 rxmaxlength; 84 uint32 txmaxlength; 85 uint32 PAD; 86 uint32 mdiocontrol; 87 uint32 mdiodata; 88 uint32 emacintmask; 89 uint32 emacintstatus; 90 uint32 camdatalo; 91 uint32 camdatahi; 92 uint32 camcontrol; 93 uint32 enetcontrol; 94 uint32 txcontrol; 95 uint32 txwatermark; 96 uint32 mibcontrol; 97 uint32 PAD[49]; 98 99 /* EMAC MIB counters */ 100 bcmenetmib_t mib; 101 102 uint32 PAD[585]; 103 104 /* Sonics SiliconBackplane config registers */ 105 sbconfig_t sbconfig; 106} bcmenetregs_t; 107 108/* device control */ 109#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */ 110#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */ 111#define DC_ER ((uint32)1 << 15) /* ephy reset */ 112#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */ 113#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */ 114#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */ 115#define DC_PA_SHIFT 18 116#define DC_FS_MASK 0x03800000 /* fifo size (rev >= 8) */ 117#define DC_FS_SHIFT 23 118#define DC_FS_4K 0 /* 4Kbytes */ 119#define DC_FS_512 1 /* 512bytes */ 120 121/* wakeup length */ 122#define WL_P0_MASK 0x7f /* pattern 0 */ 123#define WL_D0 ((uint32)1 << 7) 124#define WL_P1_MASK 0x7f00 /* pattern 1 */ 125#define WL_P1_SHIFT 8 126#define WL_D1 ((uint32)1 << 15) 127#define WL_P2_MASK 0x7f0000 /* pattern 2 */ 128#define WL_P2_SHIFT 16 129#define WL_D2 ((uint32)1 << 23) 130#define WL_P3_MASK 0x7f000000 /* pattern 3 */ 131#define WL_P3_SHIFT 24 132#define WL_D3 ((uint32)1 << 31) 133 134/* intstatus and intmask */ 135#define I_PME ((uint32)1 << 6) /* power management event */ 136#define I_TO ((uint32)1 << 7) /* general purpose timeout */ 137#define I_PC ((uint32)1 << 10) /* descriptor error */ 138#define I_PD ((uint32)1 << 11) /* data error */ 139#define I_DE ((uint32)1 << 12) /* descriptor protocol error */ 140#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */ 141#define I_RO ((uint32)1 << 14) /* receive fifo overflow */ 142#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */ 143#define I_RI ((uint32)1 << 16) /* receive interrupt */ 144#define I_XI ((uint32)1 << 24) /* transmit interrupt */ 145#define I_EM ((uint32)1 << 26) /* emac interrupt */ 146#define I_MW ((uint32)1 << 27) /* mii write */ 147#define I_MR ((uint32)1 << 28) /* mii read */ 148 149/* emaccontrol */ 150#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */ 151#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */ 152#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */ 153#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */ 154#define EMC_LC_SHIFT 5 155 156/* emacflowcontrol */ 157#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */ 158#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */ 159 160/* interrupt receive lazy */ 161#define IRL_TO_MASK 0x00ffffff /* timeout */ 162#define IRL_FC_MASK 0xff000000 /* frame count */ 163#define IRL_FC_SHIFT 24 /* frame count */ 164 165/* emac receive config */ 166#define ERC_DB ((uint32)1 << 0) /* disable broadcast */ 167#define ERC_AM ((uint32)1 << 1) /* accept all multicast */ 168#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */ 169#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */ 170#define ERC_LE ((uint32)1 << 4) /* loopback enable */ 171#define ERC_FE ((uint32)1 << 5) /* enable flow control */ 172#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */ 173#define ERC_RF ((uint32)1 << 7) /* reject filter */ 174#define ERC_CA ((uint32)1 << 8) /* cam absent */ 175 176/* emac mdio control */ 177#define MC_MF_MASK 0x7f /* mdc frequency */ 178#define MC_PE ((uint32)1 << 7) /* mii preamble enable */ 179 180/* emac mdio data */ 181#define MD_DATA_MASK 0xffff /* r/w data */ 182#define MD_TA_MASK 0x30000 /* turnaround value */ 183#define MD_TA_SHIFT 16 184#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */ 185#define MD_RA_MASK 0x7c0000 /* register address */ 186#define MD_RA_SHIFT 18 187#define MD_PMD_MASK 0xf800000 /* physical media device */ 188#define MD_PMD_SHIFT 23 189#define MD_OP_MASK 0x30000000 /* opcode */ 190#define MD_OP_SHIFT 28 191#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */ 192#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */ 193#define MD_SB_MASK 0xc0000000 /* start bits */ 194#define MD_SB_SHIFT 30 195#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */ 196 197/* emac intstatus and intmask */ 198#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */ 199#define EI_MIB ((uint32)1 << 1) /* mib interrupt */ 200#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */ 201 202/* emac cam data high */ 203#define CD_V ((uint32)1 << 16) /* valid bit */ 204 205/* emac cam control */ 206#define CC_CE ((uint32)1 << 0) /* cam enable */ 207#define CC_MS ((uint32)1 << 1) /* mask select */ 208#define CC_RD ((uint32)1 << 2) /* read */ 209#define CC_WR ((uint32)1 << 3) /* write */ 210#define CC_INDEX_MASK 0x3f0000 /* index */ 211#define CC_INDEX_SHIFT 16 212#define CC_CB ((uint32)1 << 31) /* cam busy */ 213 214/* emac ethernet control */ 215#define EC_EE ((uint32)1 << 0) /* emac enable */ 216#define EC_ED ((uint32)1 << 1) /* emac disable */ 217#define EC_ES ((uint32)1 << 2) /* emac soft reset */ 218#define EC_EP ((uint32)1 << 3) /* external phy select */ 219 220/* emac transmit control */ 221#define EXC_FD ((uint32)1 << 0) /* full duplex */ 222#define EXC_FM ((uint32)1 << 1) /* flowmode */ 223#define EXC_SB ((uint32)1 << 2) /* single backoff enable */ 224#define EXC_SS ((uint32)1 << 3) /* small slottime */ 225 226/* emac mib control */ 227#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */ 228 229#endif /* _bcmenet_47xx_h_ */ 230