1/* 2 * Copyright (c) 1995, 1996, 1999 3 * Christopher G. Demetriou. All rights reserved. 4 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _DEV_PCI_PCIREG_H_ 33#define _DEV_PCI_PCIREG_H_ 34 35/* 36 * Standardized PCI configuration register definitions and macros. 37 * Derived from information found in the ``PCI Local Bus Specification, 38 * Revision 2.2, December 18, 1998.'' 39 * 40 * Note: Register and field definitions assume 32-bit register accesses. 41 */ 42 43#if !defined(__ASSEMBLER__) 44typedef uint16_t pci_vendor_id_t; 45typedef uint16_t pci_product_id_t; 46 47typedef uint8_t pci_class_t; 48typedef uint8_t pci_subclass_t; 49typedef uint8_t pci_interface_t; 50typedef uint8_t pci_revision_t; 51 52typedef uint8_t pci_intr_latency_t; 53typedef uint8_t pci_intr_grant_t; 54typedef uint8_t pci_intr_pin_t; 55typedef uint8_t pci_intr_line_t; 56#endif 57 58/* some PCI bus constants */ 59 60#define PCI_BUSMAX 255 61#define PCI_DEVMAX 31 62#define PCI_FUNCMAX 7 63#define PCI_REGMAX 255 64 65/* 66 * Common PCI header 67 */ 68 69/* 70 * Device identification register; contains a vendor ID and a device ID. 71 */ 72#define PCI_ID_REG 0x00 73 74#define PCI_VENDOR_SHIFT 0 75#define PCI_VENDOR_MASK 0xffff 76#define PCI_VENDOR(id) \ 77 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 78 79#define PCI_PRODUCT_SHIFT 16 80#define PCI_PRODUCT_MASK 0xffff 81#define PCI_PRODUCT(id) \ 82 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 83 84/* 85 * Command and status register. 86 */ 87#define PCI_COMMAND_STATUS_REG 0x04 88 89#define PCI_COMMAND_SHIFT 0 90#define PCI_COMMAND_MASK 0xffff 91#define PCI_COMMAND(csr) \ 92 (((csr) >> PCI_COMMAND_SHIFT) & PCI_COMMAND_MASK) 93 94#define PCI_STATUS_SHIFT 16 95#define PCI_STATUS_MASK 0xffff 96#define PCI_STATUS(csr) \ 97 (((csr) >> PCI_STATUS_SHIFT) & PCI_STATUS_MASK) 98 99#define PCI_COMMAND_IO_ENABLE 0x00000001 100#define PCI_COMMAND_MEM_ENABLE 0x00000002 101#define PCI_COMMAND_MASTER_ENABLE 0x00000004 102#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 103#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 104#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 105#define PCI_COMMAND_PARITY_ENABLE 0x00000040 106#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 107#define PCI_COMMAND_SERR_ENABLE 0x00000100 108#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 109 110#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 111#define PCI_STATUS_66MHZ_SUPPORT 0x00200000 112#define PCI_STATUS_UDF_SUPPORT 0x00400000 113#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 114#define PCI_STATUS_PARITY_ERROR 0x01000000 115#define PCI_STATUS_DEVSEL_FAST 0x00000000 116#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 117#define PCI_STATUS_DEVSEL_SLOW 0x04000000 118#define PCI_STATUS_DEVSEL_MASK 0x06000000 119#define PCI_STATUS_DEVSEL_SHIFT 25 120#define PCI_STATUS_DEVSEL(scr) \ 121 (((scr) & PCI_STATUS_DEVSEL_MASK) >> PCI_STATUS_DEVSEL_SHIFT) 122#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 123#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 124#define PCI_STATUS_MASTER_ABORT 0x20000000 125#define PCI_STATUS_SYSTEM_ERROR 0x40000000 126#define PCI_STATUS_PARITY_DETECT 0x80000000 127 128/* 129 * PCI Class and Revision Register; defines type and revision of device. 130 */ 131#define PCI_CLASS_REG 0x08 132 133#define PCI_CLASS_SHIFT 24 134#define PCI_CLASS_MASK 0xff 135#define PCI_CLASS(cr) \ 136 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 137 138#define PCI_SUBCLASS_SHIFT 16 139#define PCI_SUBCLASS_MASK 0xff 140#define PCI_SUBCLASS(cr) \ 141 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 142 143#define PCI_INTERFACE_SHIFT 8 144#define PCI_INTERFACE_MASK 0xff 145#define PCI_INTERFACE(cr) \ 146 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 147 148#define PCI_REVISION_SHIFT 0 149#define PCI_REVISION_MASK 0xff 150#define PCI_REVISION(cr) \ 151 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 152 153#define PCI_CLASS_CODE(class, subclass, interface) \ 154 ((((class) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ 155 (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ 156 (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) 157 158/* base classes */ 159#define PCI_CLASS_PREHISTORIC 0x00 160#define PCI_CLASS_MASS_STORAGE 0x01 161#define PCI_CLASS_NETWORK 0x02 162#define PCI_CLASS_DISPLAY 0x03 163#define PCI_CLASS_MULTIMEDIA 0x04 164#define PCI_CLASS_MEMORY 0x05 165#define PCI_CLASS_BRIDGE 0x06 166#define PCI_CLASS_COMMUNICATIONS 0x07 167#define PCI_CLASS_SYSTEM 0x08 168#define PCI_CLASS_INPUT 0x09 169#define PCI_CLASS_DOCK 0x0a 170#define PCI_CLASS_PROCESSOR 0x0b 171#define PCI_CLASS_SERIALBUS 0x0c 172#define PCI_CLASS_WIRELESS 0x0d 173#define PCI_CLASS_I2O 0x0e 174#define PCI_CLASS_SATCOM 0x0f 175#define PCI_CLASS_CRYPTO 0x10 176#define PCI_CLASS_DASP 0x11 177#define PCI_CLASS_UNDEFINED 0xff 178 179/* 0x00 prehistoric subclasses */ 180#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 181#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 182 183/* 0x01 mass storage subclasses */ 184#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 185#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 186#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 187#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 188#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 189#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 190 191/* 0x02 network subclasses */ 192#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 193#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 194#define PCI_SUBCLASS_NETWORK_FDDI 0x02 195#define PCI_SUBCLASS_NETWORK_ATM 0x03 196#define PCI_SUBCLASS_NETWORK_ISDN 0x04 197#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 198#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 199#define PCI_SUBCLASS_NETWORK_MISC 0x80 200 201/* 0x03 display subclasses */ 202#define PCI_SUBCLASS_DISPLAY_VGA 0x00 203#define PCI_SUBCLASS_DISPLAY_XGA 0x01 204#define PCI_SUBCLASS_DISPLAY_3D 0x02 205#define PCI_SUBCLASS_DISPLAY_MISC 0x80 206 207/* 0x04 multimedia subclasses */ 208#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 209#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 210#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 211#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 212 213/* 0x05 memory subclasses */ 214#define PCI_SUBCLASS_MEMORY_RAM 0x00 215#define PCI_SUBCLASS_MEMORY_FLASH 0x01 216#define PCI_SUBCLASS_MEMORY_MISC 0x80 217 218/* 0x06 bridge subclasses */ 219#define PCI_SUBCLASS_BRIDGE_HOST 0x00 220#define PCI_SUBCLASS_BRIDGE_ISA 0x01 221#define PCI_SUBCLASS_BRIDGE_EISA 0x02 222#define PCI_SUBCLASS_BRIDGE_MCA 0x03 223#define PCI_SUBCLASS_BRIDGE_PCI 0x04 224#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 225#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 226#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 227#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 228#define PCI_SUBCLASS_BRIDGE_STPCI 0x09 229#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 230#define PCI_SUBCLASS_BRIDGE_MISC 0x80 231 232/* 0x07 communications subclasses */ 233#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 234#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 235#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 236#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 237#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 238 239/* 0x08 system subclasses */ 240#define PCI_SUBCLASS_SYSTEM_PIC 0x00 241#define PCI_SUBCLASS_SYSTEM_DMA 0x01 242#define PCI_SUBCLASS_SYSTEM_TIMER 0x02 243#define PCI_SUBCLASS_SYSTEM_RTC 0x03 244#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 245#define PCI_SUBCLASS_SYSTEM_MISC 0x80 246 247/* 0x09 input subclasses */ 248#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 249#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 250#define PCI_SUBCLASS_INPUT_MOUSE 0x02 251#define PCI_SUBCLASS_INPUT_SCANNER 0x03 252#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 253#define PCI_SUBCLASS_INPUT_MISC 0x80 254 255/* 0x0a dock subclasses */ 256#define PCI_SUBCLASS_DOCK_GENERIC 0x00 257#define PCI_SUBCLASS_DOCK_MISC 0x80 258 259/* 0x0b processor subclasses */ 260#define PCI_SUBCLASS_PROCESSOR_386 0x00 261#define PCI_SUBCLASS_PROCESSOR_486 0x01 262#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 263#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 264#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 265#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 266#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 267 268/* 0x0c serial bus subclasses */ 269#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 270#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 271#define PCI_SUBCLASS_SERIALBUS_SSA 0x02 272#define PCI_SUBCLASS_SERIALBUS_USB 0x03 273#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 274#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 275#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 276#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 277#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 278#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 279 280/* 0x0d wireless subclasses */ 281#define PCI_SUBCLASS_WIRELESS_IRDA 0x00 282#define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 283#define PCI_SUBCLASS_WIRELESS_RF 0x10 284#define PCI_SUBCLASS_WIRELESS_MISC 0x80 285 286/* 0x0e I2O (Intelligent I/O) subclasses */ 287#define PCI_SUBCLASS_I2O_STANDARD 0x00 288 289/* 0x0f satellite communication subclasses */ 290#define PCI_SUBCLASS_SATCOM_TV 0x01 291#define PCI_SUBCLASS_SATCOM_AUDIO 0x02 292#define PCI_SUBCLASS_SATCOM_VOICE 0x03 293#define PCI_SUBCLASS_SATCOM_DATA 0x04 294 295/* 0x10 encryption/decryption subclasses */ 296#define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 297#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 298#define PCI_SUBCLASS_CRYPTO_MISC 0x80 299 300/* 0x11 data acquisition and signal processing subclasses */ 301#define PCI_SUBCLASS_DASP_DPIO 0x00 302#define PCI_SUBCLASS_DASP_TIMERFREQ 0x01 303#define PCI_SUBCLASS_DASP_MISC 0x80 304 305/* 306 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 307 */ 308#define PCI_BHLC_REG 0x0c 309 310#define PCI_BIST_SHIFT 24 311#define PCI_BIST_MASK 0xff 312#define PCI_BIST(bhlcr) \ 313 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 314 315#define PCI_HDRTYPE_SHIFT 16 316#define PCI_HDRTYPE_MASK 0xff 317#define PCI_HDRTYPE(bhlcr) \ 318 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 319 320#define PCI_HDRTYPE_TYPE(bhlcr) \ 321 (PCI_HDRTYPE(bhlcr) & 0x7f) 322#define PCI_HDRTYPE_MULTIFN(bhlcr) \ 323 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 324 325#define PCI_LATTIMER_SHIFT 8 326#define PCI_LATTIMER_MASK 0xff 327#define PCI_LATTIMER(bhlcr) \ 328 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 329#define PCI_LATTIMER_SET(bhlcr,v) \ 330 (bhlcr) = ((bhlcr) & ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT)) | \ 331 ((v) << PCI_LATTIMER_SHIFT) 332 333#define PCI_CACHELINE_SHIFT 0 334#define PCI_CACHELINE_MASK 0xff 335#define PCI_CACHELINE(bhlcr) \ 336 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 337#define PCI_CACHELINE_SET(bhlcr,v) \ 338 (bhlcr) = ((bhlcr) & ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)) | \ 339 ((v) << PCI_CACHELINE_SHIFT) 340 341/* 342 * The currently defined header types are 343 * 00h prefix PCI_ below 344 * 01h prefix PPB_ below (PCI-to-PCI bridges) 345 * 02h prefix PCB_ below (Cardbus bridges) 346 */ 347 348/* 349 * Type 00h Configuration Space extensions. 350 */ 351 352/* 353 * Mapping registers 354 */ 355#define PCI_MAPREG_START 0x10 356#define PCI_MAPREG_END 0x28 357 358#define PCI_MAPREG_PPB_END 0x18 359#define PCI_MAPREG_PPB_ROM 0x38 360#define PCI_MAPREG_PCB_END 0x14 361#define PCI_MAPREG_NONE 0x00 362 363#define PCI_MAPREG_TYPE(mr) \ 364 ((mr) & PCI_MAPREG_TYPE_MASK) 365#define PCI_MAPREG_TYPE_MASK 0x00000001 366 367#define PCI_MAPREG_TYPE_MEM 0x00000000 368#define PCI_MAPREG_TYPE_IO 0x00000001 369 370#define PCI_MAPREG_MEM_TYPE(mr) \ 371 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 372#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 373 374#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 375#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 376#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 377 378#define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 379 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 380#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 381 382#define PCI_MAPREG_MEM_ADDR(mr) \ 383 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 384#define PCI_MAPREG_MEM_SIZE(mr) \ 385 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 386#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 387 388#define PCI_MAPREG_MEM64_ADDR(mr) \ 389 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 390#define PCI_MAPREG_MEM64_SIZE(mr) \ 391 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 392#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 393 394#define PCI_MAPREG_IO_ADDR(mr) \ 395 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 396#define PCI_MAPREG_IO_SIZE(mr) \ 397 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 398#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc 399 400#define PCI_MAPREG_SIZE_TO_MASK(size) \ 401 (-(size)) 402 403#define PCI_MAPREG(num) (PCI_MAPREG_START + 4*(num)) 404#define PCI_MAPREG_NUM(offset) \ 405 (((unsigned)(offset)-PCI_MAPREG_START)/4) 406 407/* 408 * Cardbus CIS pointer (PCI rev. 2.1) 409 */ 410#define PCI_CARDBUS_CIS_REG 0x28 411 412/* 413 * Subsystem identification register; contains a vendor ID and a device ID. 414 * Types/macros for PCI_ID_REG apply. 415 * (PCI rev. 2.1) 416 */ 417#define PCI_SUBSYS_ID_REG 0x2c 418 419/* 420 * Expansion ROM base address register; contains an address and enable bit. 421 */ 422#define PCI_MAPREG_ROM 0x30 423#define PCI_MAPREG_ROM_ADDR(mr) \ 424 ((mr) & PCI_MAPREG_ROM_ADDR_MASK) 425#define PCI_MAPREG_ROM_ADDR_MASK 0xfffff800 426#define PCI_MAPREG_ROM_ENABLE 0x00000001 427 428/* 429 * capabilities link list (PCI rev. 2.2) 430 */ 431#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 432#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 433#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 434#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 435#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 436 437#define PCI_CAP_RESERVED0 0x00 438#define PCI_CAP_PWRMGMT 0x01 439#define PCI_CAP_AGP 0x02 440#define PCI_CAP_VPD 0x03 441#define PCI_CAP_SLOTID 0x04 442#define PCI_CAP_MBI 0x05 443#define PCI_CAP_CPCI_HOTSWAP 0x06 444#define PCI_CAP_PCIX 0x07 445#define PCI_CAP_LDT 0x08 446#define PCI_CAP_VENDSPEC 0x09 447#define PCI_CAP_DEBUGPORT 0x0a 448#define PCI_CAP_CPCI_RSRCCTL 0x0b 449#define PCI_CAP_HOTPLUG 0x0c 450 451/* 452 * Power Management Control Status Register; access via capability pointer. 453 */ 454#define PCI_PMCSR_STATE_MASK 0x03 455#define PCI_PMCSR_STATE_D0 0x00 456#define PCI_PMCSR_STATE_D1 0x01 457#define PCI_PMCSR_STATE_D2 0x02 458#define PCI_PMCSR_STATE_D3 0x03 459 460/* 461 * Bus Parameter and Interrupt Configuration Register; 462 * contains interrupt pin and line. 463 */ 464#define PCI_BPARAM_INTERRUPT_REG 0x3c 465 466#define PCI_BPARAM_LATENCY_SHIFT 24 467#define PCI_BPARAM_LATENCY_MASK 0xff 468#define PCI_BPARAM_LATENCY(bpir) \ 469 (((bpir) >> PCI_BPARAM_LATENCY_SHIFT) & PCI_BPARAM_LATENCY_MASK) 470 471#define PCI_BPARAM_GRANT_SHIFT 16 472#define PCI_BPARAM_GRANT_MASK 0xff 473#define PCI_BPARAM_GRANT(bpir) \ 474 (((bpir) >> PCI_BPARAM_GRANT_SHIFT) & PCI_BPARAM_GRANT_MASK) 475 476#define PCI_INTERRUPT_PIN_SHIFT 8 477#define PCI_INTERRUPT_PIN_MASK 0xff 478#define PCI_INTERRUPT_PIN(bpir) \ 479 (((bpir) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 480 481#define PCI_INTERRUPT_LINE_SHIFT 0 482#define PCI_INTERRUPT_LINE_MASK 0xff 483#define PCI_INTERRUPT_LINE(bpir) \ 484 (((bpir) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 485 486#define PCI_INTERRUPT_PIN_NONE 0x00 487#define PCI_INTERRUPT_PIN_A 0x01 488#define PCI_INTERRUPT_PIN_B 0x02 489#define PCI_INTERRUPT_PIN_C 0x03 490#define PCI_INTERRUPT_PIN_D 0x04 491#define PCI_INTERRUPT_PIN_MAX 0x04 492 493 494/* 495 * Type 01h Configuration Space extension: 496 * PCI to PCI Bridge registers (cf ppbreg.h) 497 * Derived from information found in the ``PCI to PCI Bridge 498 * Architecture Specification, Revision 1.1, December 18, 1998.'' 499 */ 500 501#define PPB_MAPREG_START 0x10 502#define PPB_MAPREG_END 0x18 503 504/* 505 * Bus Information Register; contains bus hierarchy and secondary latency. 506 */ 507#define PPB_BUSINFO_REG 0x18 508 509#define PPB_BUSINFO_LATENCY_SHIFT 24 510#define PPB_BUSINFO_LATENCY_MASK 0xff 511#define PPB_BUSINFO_LATENCY(br) \ 512 (((br) >> PPB_BUSINFO_LATENCY_SHIFT) & PPB_BUSINFO_LATENCY_MASK) 513 514#define PPB_BUSINFO_SUBORD_SHIFT 16 515#define PPB_BUSINFO_SUBORD_MASK 0xff 516#define PPB_BUSINFO_SUBORD(br) \ 517 (((br) >> PPB_BUSINFO_SUBORD_SHIFT) & PPB_BUSINFO_SUBORD_MASK) 518 519#define PPB_BUSINFO_SECONDARY_SHIFT 8 520#define PPB_BUSINFO_SECONDARY_MASK 0xff 521#define PPB_BUSINFO_SECONDARY(br) \ 522 (((br) >> PPB_BUSINFO_SECONDARY_SHIFT) & PPB_BUSINFO_SECONDARY_MASK) 523 524#define PPB_BUSINFO_PRIMARY_SHIFT 0 525#define PPB_BUSINFO_PRIMARY_MASK 0xff 526#define PPB_BUSINFO_PRIMARY(br) \ 527 (((br) >> PPB_BUSINFO_PRIMARY_SHIFT) & PPB_BUSINFO_PRIMARY_MASK) 528 529/* 530 * IO Status Register; contains I/O base + limit and secondary status. 531 * Masks/macros for PCI_STATUS apply to Secondary Status. 532 */ 533#define PPB_IO_STATUS_REG 0x1C 534 535#define PPB_IO_BASE_MASK 0x000000ff 536#define PPB_IO_LIMIT_MASK 0x0000ff00 537#define PPB_IO_ADDR_CAP_MASK 0x00000f0f 538#define PPB_IO_ADDR_CAP_16 0x00000000 539#define PPB_IO_ADDR_CAP_32 0x00000101 540#define PPB_IO_BASE(iosr) \ 541 (((iosr) >> 0) & 0xff) 542#define PPB_IO_LIMIT(iosr) \ 543 (((iosr) >> 8) & 0xff) 544 545#define PPB_SECSTATUS_SHIFT 16 546#define PPB_SECSTATUS_MASK 0xffff 547#define PPB_SECSTATUS(iosr) \ 548 (((iosr) >> PPB_SECSTATUS_SHIFT) & PPB_SECSTATUS_MASK) 549 550/* 551 * Base and limit values for address ranges have common packing. 552 */ 553#define PPB_BASE_SHIFT 0 554#define PPB_BASE_MASK 0xffff 555#define PPB_BASE(blr) \ 556 (((blr) >> PPB_BASE_SHIFT) & PPB_BASE_MASK) 557 558#define PPB_LIMIT_SHIFT 16 559#define PPB_LIMIT_MASK 0xffff 560#define PPB_LIMIT(blr) \ 561 (((blr) >> PPB_LIMIT_SHIFT) & PPB_LIMIT_MASK) 562 563/* 564 * Memory Registers; contains memory base + limit. 565 */ 566#define PPB_MEM_REG 0x20 567#define PPB_PREFMEM_REG 0x24 568 569#define PPB_MEM_BASE_MASK 0x0000ffff 570#define PPB_MEM_LIMIT_MASK 0xffff0000 571 572/* 573 * Prefetchable Memory Upper Registers; contain high bits 574 */ 575#define PPB_PREFMEM_BASE_UPPER_REG 0x28 576#define PPB_PREFMEM_LIMIT_UPPER_REG 0x2c 577 578/* 579 * IO Upper Register; contains I/O base + limit high bits 580 */ 581#define PPB_IO_UPPER_REG 0x30 582 583#define PPB_IO_UPPER_BASE_MASK 0x0000ffff 584#define PPB_IO_UPPER_LIMIT_MASK 0xffff0000 585 586/* 587 * Expansion ROM Base Address Register. 588 */ 589#define PPB_MAPREG_ROM 0x38 590 591/* 592 * Bridge Control and Interrupt Register 593 * Masks/macros for PCI_INTERRUPT apply to Interrupt 594 */ 595#define PPB_BRCTL_INTERRUPT_REG 0x3C 596 597#define PPB_BRCTL_SHIFT 16 598#define PPB_BRCTL_MASK 0xffff 599#define PPB_BRCTL(bcir) \ 600 (((bcir) >> PPB_BRCTL_SHIFT) & PPB_BRCTL_MASK) 601 602#define PPB_BRCTL_PARITY_ENABLE 0x00010000 603#define PPB_BRCTL_SERR_ENABLE 0x00020000 604#define PPB_BRCTL_ISA_ENABLE 0x00040000 605#define PPB_BRCTL_VGA_ENABLE 0x00080000 606#define PPB_BRCTL_MASTER_ABORT_MODE 0x00200000 607#define PPB_BRCTL_SECONDARY_RESET 0x00400000 608#define PPB_BRCTL_BACKTOBACK_ENABLE 0x00800000 609#define PPB_BRCTL_PRIMARY_DISCARD_TIMER 0x01000000 610#define PPB_BRCTL_SECONDARY_DISCARD_TIMER 0x02000000 611#define PPB_BRCTL_DISCARD_TIMER_STATUS 0x04000000 612#define PPB_BRCTL_DISCARD_SERR_ENABLE 0x08000000 613 614#endif /* _DEV_PCI_PCIREG_H_ */ 615