1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * BCM1250-specific PCI support File: sb1250_pci_machdep.c 5 * 6 ********************************************************************* 7 * 8 * Copyright 2001,2002,2003 9 * Broadcom Corporation. All rights reserved. 10 * 11 * This software is furnished under license and may be used and 12 * copied only in accordance with the following terms and 13 * conditions. Subject to these conditions, you may download, 14 * copy, install, use, modify and distribute modified or unmodified 15 * copies of this software in source and/or binary form. No title 16 * or ownership is transferred hereby. 17 * 18 * 1) Any source code used, modified or distributed must reproduce 19 * and retain this copyright notice and list of conditions 20 * as they appear in the source file. 21 * 22 * 2) No right is granted to use any trade name, trademark, or 23 * logo of Broadcom Corporation. The "Broadcom Corporation" 24 * name may not be used to endorse or promote products derived 25 * from this software without the prior written permission of 26 * Broadcom Corporation. 27 * 28 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 30 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 31 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 32 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 33 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 38 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 39 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 40 * THE POSSIBILITY OF SUCH DAMAGE. 41 ********************************************************************* */ 42 43/* 44 * Based in part on the algor p5064 version of pci_machdep.c, 45 * from SiByte sources dated 20000824. 46 */ 47 48/* Very loosely based on: */ 49/* $NetBSD: pci_machdep.c,v 1.17 1995/07/27 21:39:59 cgd Exp $ */ 50 51/* 52 * Copyright (c) 1994 Charles Hannum. All rights reserved. 53 * 54 * Redistribution and use in source and binary forms, with or without 55 * modification, are permitted provided that the following conditions 56 * are met: 57 * 1. Redistributions of source code must retain the above copyright 58 * notice, this list of conditions and the following disclaimer. 59 * 2. Redistributions in binary form must reproduce the above copyright 60 * notice, this list of conditions and the following disclaimer in the 61 * documentation and/or other materials provided with the distribution. 62 * 3. All advertising materials mentioning features or use of this software 63 * must display the following acknowledgement: 64 * This product includes software developed by Charles Hannum. 65 * 4. The name of the author may not be used to endorse or promote products 66 * derived from this software without specific prior written permission. 67 * 68 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 69 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 70 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 71 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 72 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 73 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 74 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 75 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 76 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 77 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 80/* 81 * Sibyte SB-1250 machine-specific functions for PCI autoconfiguration. 82 */ 83 84#include "lib_types.h" 85#include "lib_string.h" 86#include "lib_printf.h" 87#include "bsp_config.h" 88#include "cfe.h" 89#include "sbmips.h" 90#include "sb1250_defs.h" 91#include "sb1250_regs.h" 92#include "sb1250_scd.h" 93#include "lib_physio.h" 94#include "cfe_timer.h" 95#include "env_subr.h" 96extern void cfe_ledstr(const char *); 97 98#include "pcivar.h" 99#include "pcireg.h" 100#include "ldtreg.h" 101 102#define SBD_DISPLAY(msg) cfe_ledstr(msg) 103 104const cons_t pci_optnames[] = { 105 {"verbose",PCI_FLG_VERBOSE}, 106 {"ldt_prefetch",PCI_FLG_LDT_PREFETCH}, 107 {"ldt_rev_017",PCI_FLG_LDT_REV_017}, 108 {NULL,0} 109}; 110 111extern int _pciverbose; 112 113 114/* PCI regions in system physical (ZBbus) space. See Figure 37. */ 115 116static struct { 117 /* ZBbus space allocated for mapping to the standard PCI address spaces */ 118 uint32_t mem_space; 119 uint32_t mem_space_size; 120 uint32_t io_space; 121 uint32_t io_space_size; 122 uint32_t cfg_space; 123 uint32_t cfg_space_size; 124 125 /* PCI space available for configuration */ 126 uint32_t pci_mem_base; 127 uint32_t pci_io_base; 128 129 /* Bits for endian policy (0: match bytes, 1: match bits) */ 130 uint32_t mem_bit_endian; 131 uint32_t io_bit_endian; 132 uint32_t cfg_bit_endian; 133 134 /* Match bits base for configuration (convenience variable) */ 135 physaddr_t cfg_base; 136} Q; 137 138static void 139pci_set_root (void) 140{ 141 Q.mem_space = A_PHYS_LDTPCI_IO_MATCH_BYTES_32; /* 0x0040000000 */ 142 Q.mem_space_size = 0x0020000000; 143 Q.io_space = A_PHYS_LDTPCI_IO_MATCH_BYTES; /* 0x00DC000000 */ 144 Q.io_space_size = 0x0002000000; 145 Q.cfg_space = A_PHYS_LDTPCI_CFG_MATCH_BYTES; /* 0x00DE000000 */ 146 Q.cfg_space_size = 0x0001000000; 147 148 Q.pci_mem_base = 0x40000000; 149 Q.pci_io_base = 0x00000000; 150 151 Q.mem_bit_endian = 0x0020000000; 152 Q.io_bit_endian = 0x0020000000; 153 Q.cfg_bit_endian = 0x0020000000; 154 155 Q.cfg_base = PHYS_TO_XKSEG_UNCACHED(Q.cfg_space | Q.cfg_bit_endian); 156} 157 158 159/* Templates for bus attributes. */ 160 161static const struct pci_bus sb1250_pci_bus = { 162 0, /* minimum grant */ 163 255, /* maximum latency */ 164 1, /* devsel time = medium */ 165 1, /* we support fast back-to-back */ 166 1, /* we support prefetch */ 167 1, /* we support 66 MHz */ 168 0, /* we don't support 64 bits */ 169 4000000, /* bandwidth: in 0.25us cycles / sec */ 170 0, /* initially no devices on bus */ 171}; 172 173static const struct pci_bus secondary_pci_bus = { 174 0, /* minimum grant */ 175 255, /* maximum latency */ 176 0, /* devsel time = unknown */ 177 0, /* configure fast back-to-back */ 178 0, /* we don't prefetch */ 179 0, /* configure 66 MHz */ 180 0, /* we don't support 64 bits */ 181 4000000, /* bandwidth: in 0.25us cycles / sec */ 182 0, /* initially no devices on bus */ 183}; 184 185#define MAXBUS 10 186static struct pci_bus _pci_bus[MAXBUS]; 187static int _pci_nbus = 0; 188 189#define SB1250_PCI_MAKE_TAG(b,d,f) \ 190 (((b) << 16) | ((d) << 11) | ((f) << 8)) 191 192#if defined(__MIPSEB) 193/* This is for big-endian with a match bits policy. */ 194#define SB1250_CFG_ADDR(t, o, w) \ 195 ((Q.cfg_base + (t) + (o)) ^ (4 - (w))) 196#elif defined(__MIPSEL) 197/* This is for little-endian, either policy. */ 198#define SB1250_CFG_ADDR(t, o, w) \ 199 (Q.cfg_base + (t) + (o)) 200#else 201#error "Must specifiy either MIPSEL or MIPSEB" 202#endif 203 204pcireg_t pci_conf_read8(pcitag_t, int); 205void pci_conf_write8(pcitag_t, int, pcireg_t); 206#ifndef pci_conf_read32 207#define pci_conf_read32 pci_conf_read 208#endif 209#ifndef pci_conf_write32 210#define pci_conf_write32 pci_conf_write 211#endif 212 213 214/* Access functions */ 215 216/* The following must either fail or return the next sequential bus 217 number to make secondary/subordinate numbering work correctly. */ 218int 219pci_nextbus (int port) 220{ 221 int bus = _pci_nbus; 222 223 if (bus >= MAXBUS) 224 return -1; 225 _pci_nbus++; 226 return bus; 227} 228 229int 230pci_maxbus (int port) 231{ 232 return _pci_nbus - 1; 233} 234 235struct pci_bus * 236pci_businfo (int port, int bus) 237{ 238 return (bus < _pci_nbus ? &_pci_bus[bus] : NULL); 239} 240 241/* 242 * PCI address resources. 243 * NB: initial limits for address allocation are assumed to be aligned 244 * appropriately for PCI bridges (4K boundaries for I/O, 1M for memory). 245 */ 246 247pcireg_t 248pci_minmemaddr (int port) 249{ 250 /* skip the 16MB reserved for ISA mem space */ 251 return Q.pci_mem_base + 0x1000000; 252} 253 254pcireg_t 255pci_maxmemaddr (int port) 256{ 257 return Q.pci_mem_base + Q.mem_space_size; 258} 259 260pcireg_t 261pci_minioaddr (int port) 262{ 263 /* Skip the 32KB reserved for ISA i/o space. */ 264 return Q.pci_io_base + 0x8000; 265} 266 267pcireg_t 268pci_maxioaddr (int port) 269{ 270 return Q.pci_io_base + Q.io_space_size; 271} 272 273 274/* The SB-1250 integrated host bridges. */ 275 276#define PCI_VENDOR_SIBYTE 0x166d 277 278#define SB1250_PCI_BRIDGE (SB1250_PCI_MAKE_TAG(0,0,0)) 279#define SB1250_LDT_BRIDGE (SB1250_PCI_MAKE_TAG(0,1,0)) 280 281static int sb1250_in_device_mode; 282static int sb1250_ldt_slave_mode; 283static int sb1250_ldt_init; /* Set to one after LHB sees InitDone */ 284 285/* The pass 1 BCM1250 does not implement EOI cycles correctly. Later 286 passes do. The following variable controls whether PCI interrupt 287 mappings are programmed to be level-sensitive (EOI) or 288 edge-sensitive (no EOI) in LDT-PCI bridges. */ 289int eoi_implemented; 290 291 292/* Implementation-specific registers for the PCI Host Bridge (PHB) */ 293 294#define PHB_FEATURE_REG 0x40 295 296#define PHB_FEATURE_DEFAULTS 0x7db38080 297 298#define PHB_MAP_REG_BASE 0x44 299#define PHB_MAP_N_ENTRIES 16 300 301/* The format of MAP table entries */ 302#define PHB_MAP_ENABLE (1 << 0) 303#define PHB_MAP_SEND_LDT (1 << 1) 304#define PHB_MAP_L2CA (1 << 2) 305#define PHB_MAP_ENDIAN (1 << 3) 306#define PHB_MAP_ADDR_SHIFT 12 307#define PHB_MAP_ADDR_MASK 0xfffff000 308#define PHB_MAP_ENTRY_SPAN (1 << 20) 309 310#define PHB_ERRORADDR_REG 0x84 311 312#define PHB_ADD_STAT_CMD_REG 0x88 313 314#define PHB_SUBSYSSET_REG 0x8c 315 316/* pass 2 additions */ 317 318#define PHB_READHOST_REG 0x94 319 320#define PHB_READHOST_DISABLE (0 << 0) /* write only */ 321#define PHB_READHOST_ENABLE (1 << 0) 322 323#define PHB_ADAPTEXT_REG 0x98 324 325 326/* PCI host bridge configuration 327 * 328 * Note that the PCI host bridge has two, mostly disjoint, sets of 329 * configuration registers. One is used in Host mode and is 330 * accessible from the ZBbus; the other is used in Device mode and is 331 * accessible from the PCI bus. The MAP registers are shared but in 332 * Pass 1 are write-only, from the ZBbus side. In pass 2, they are 333 * readable iff read_host is set. 334 */ 335static void 336phb_init (void) 337{ 338 int i; 339 pcireg_t csr, cr, icr; 340 pcireg_t t; /* used for reads that push writes */ 341 342 /* reset the PCI busses */ 343 /* PCI is only reset at system reset */ 344 345 /* PCI: disable and clear the BAR0 MAP registers */ 346 for (i = 0; i < PHB_MAP_N_ENTRIES; i++) 347 pci_conf_write32(SB1250_PCI_BRIDGE, PHB_MAP_REG_BASE + 4*i, 0); 348 349 /* Because they write to the ZBbus bank of configuration 350 registers, some of the following initializations are noops in 351 Device mode, but they do no harm. */ 352 353 /* PCI: set feature and timeout registers to their default. */ 354 pci_conf_write32(SB1250_PCI_BRIDGE, PHB_FEATURE_REG, PHB_FEATURE_DEFAULTS); 355 356 /* PCI: enable bridge to PCI and PCI memory accesses, including 357 write-invalidate, plus error handling */ 358 csr = PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE | 359 PCI_COMMAND_INVALIDATE_ENABLE | 360 PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE; 361 pci_conf_write32(SB1250_PCI_BRIDGE, PCI_COMMAND_STATUS_REG, csr); 362 363 /* PCI: clear errors */ 364 csr = pci_conf_read32(SB1250_PCI_BRIDGE, PCI_COMMAND_STATUS_REG); 365 csr |= PCI_STATUS_PARITY_ERROR | PCI_STATUS_SYSTEM_ERROR | 366 PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT | 367 PCI_STATUS_TARGET_TARGET_ABORT | PCI_STATUS_PARITY_DETECT; 368 pci_conf_write32(SB1250_PCI_BRIDGE, PCI_COMMAND_STATUS_REG, csr); 369 370 /* PCI: set up interrupt mapping */ 371 icr = pci_conf_read(SB1250_PCI_BRIDGE, PCI_BPARAM_INTERRUPT_REG); 372 icr &=~ (PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 373 icr |= (pci_int_line(pci_int_map_0(SB1250_PCI_BRIDGE)) 374 << PCI_INTERRUPT_LINE_SHIFT); 375 pci_conf_write32(SB1250_PCI_BRIDGE, PCI_BPARAM_INTERRUPT_REG, icr); 376 377 /* PCI: push the writes */ 378 t = pci_conf_read32(SB1250_PCI_BRIDGE, PCI_ID_REG); 379 380 cr = pci_conf_read32(SB1250_PCI_BRIDGE, PCI_CLASS_REG); 381 if (PCI_REVISION(cr) >= 2) { 382 pcireg_t id; 383 384 id = pci_conf_read32(SB1250_PCI_BRIDGE, PCI_ID_REG); 385 pci_conf_write32(SB1250_PCI_BRIDGE, PHB_SUBSYSSET_REG, id); 386 pci_conf_write32(SB1250_PCI_BRIDGE, PHB_READHOST_REG, 387 PHB_READHOST_DISABLE); 388 t = pci_conf_read32(SB1250_PCI_BRIDGE, PHB_READHOST_REG); /* push */ 389 } 390} 391 392 393/* Implementation-specific registers for the LDT Host Bridge (LHB) */ 394 395#define LHB_LINK_BASE 0x40 396 397#define LHB_LINKCMD_REG (LHB_LINK_BASE+LDT_COMMAND_CAP_OFF) 398 399#define LHB_LINKCTRL_REG (LHB_LINK_BASE+LDT_LINK_OFF(0)) 400 401#define LHB_LINKCTRL_CRCERROR (1 << LDT_LINKCTRL_CRCERROR_SHIFT) 402#define LHB_LINKCTRL_ERRORS (LHB_LINKCTRL_CRCERROR | \ 403 LDT_LINKCTRL_LINKFAIL) 404 405#define LHB_LINKFREQ_REG (LHB_LINK_BASE+LDT_FREQ_OFF) 406#define LHB_LFREQ_REG (LHB_LINKFREQ_REG+1) 407 408#define LHB_LFREQ_200 LDT_FREQ_200 /* 200 MHz */ 409#define LHB_LFREQ_300 LDT_FREQ_300 /* 300 MHz */ 410#define LHB_LFREQ_400 LDT_FREQ_400 /* 400 MHz */ 411#define LHB_LFREQ_500 LDT_FREQ_500 /* 500 MHz */ 412#define LHB_LFREQ_600 LDT_FREQ_600 /* 600 MHz */ 413#define LHB_LFREQ_800 LDT_FREQ_800 /* 800 MHz */ 414 415#define LHB_SRI_CMD_REG 0x50 416 417#define LHB_SRI_CMD_SIPREADY (1 << 16) 418#define LHB_SRI_CMD_SYNCPTRCTL (1 << 17) 419#define LHB_SRI_CMD_REDUCESYNCZERO (1 << 18) 420#define LHB_SRI_CMD_DISSTARVATIONCNT (1 << 19) 421#define LHB_SRI_CMD_RXMARGIN_SHIFT 20 422#define LHB_SRI_CMD_RXMARGIN_MASK (0x1F << LHB_SRI_CMD_RXMARGIN_SHIFT) 423#define LHB_SRI_CMD_PLLCOMPAT (1 << 25) 424#define LHB_SRI_CMD_TXOFFSET_SHIFT 28 425#define LHB_SRI_CMD_TXOFFSET_MASK (0x7 << LHB_SRI_CMD_TXOFFSET_SHIFT) 426#define LHB_SRI_CMD_LINKFREQDIRECT (1 << 31) 427 428#define LHB_SRI_TXNUM_REG 0x54 429#define LHB_SRI_RXNUM_REG 0x58 430 431#define LHB_ERR_CTRL_REG 0x68 432 433#define LHB_ERR_CTRL 0x00ffffff 434#define LHB_ERR_STATUS 0xff000000 435 436#define LHB_SRI_CTRL_REG 0x6c 437 438#define LHB_ASTAT_REG 0x70 439 440#define LHB_ASTAT_TGTDONE_SHIFT 0 441#define LHB_ASTAT_TGTDONE_MASK (0xFF << LHB_ASTAT_TGTDONE_SHIFT) 442 443#define LHB_TXBUFCNT_REG 0xc8 444 445#if (LDT_DEBUG > 1) 446static void 447show_ldt_status (void) 448{ 449 pcireg_t cmd; 450 451 cmd = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_SRI_CMD_REG); 452 xprintf(" SriCmd %04x\n", (cmd >> 16) & 0xffff); 453 xprintf(" TXNum %08x TxDen %02x RxNum %08x RxDen %02x ErrCtl %08x\n", 454 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_SRI_TXNUM_REG), 455 cmd & 0xff, 456 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_SRI_RXNUM_REG), 457 (cmd >> 8) & 0xff, 458 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG)); 459 xprintf(" LDTCmd %08x LDTCfg %08x LDTFreq %08x\n", 460 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCMD_REG), 461 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG), 462 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKFREQ_REG)); 463} 464#else 465#define show_ldt_status() ((void)0) 466#endif /* LDT_DEBUG */ 467 468/* 469 * Assert warm reset for the given number of ticks. 470 */ 471static void 472lhb_link_reset (int delay) 473{ 474 pcireg_t prev, cmd; 475 pcireg_t brctrl; 476 477 prev = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCMD_REG); 478 cmd = prev | LDT_COMMAND_WARM_RESET; 479 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_LINKCMD_REG, cmd); 480 481 brctrl = pci_conf_read32(SB1250_LDT_BRIDGE, PPB_BRCTL_INTERRUPT_REG); 482 brctrl |= PPB_BRCTL_SECONDARY_RESET; 483 pci_conf_write32(SB1250_LDT_BRIDGE, PPB_BRCTL_INTERRUPT_REG, brctrl); 484 485 cfe_sleep(delay); 486 487 brctrl &=~ PPB_BRCTL_SECONDARY_RESET; 488 pci_conf_write32(SB1250_LDT_BRIDGE, PPB_BRCTL_INTERRUPT_REG, brctrl); 489 brctrl = pci_conf_read32(SB1250_LDT_BRIDGE, PPB_BRCTL_INTERRUPT_REG); 490 491 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_LINKCMD_REG, prev); 492} 493 494/* 495 * Poll for InitDone on LHB's outgoing link. 496 */ 497static int 498lhb_link_ready (int maxpoll) 499{ 500 volatile pcireg_t ctrl; 501 int count; 502 int linkerr; 503 504 count = 0; 505 linkerr = 0; 506 ctrl = 0; 507 508 while ((ctrl & (LDT_LINKCTRL_INITDONE | LDT_LINKCTRL_LINKFAIL)) == 0 509 && count < maxpoll) { 510 ctrl = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG); 511 count++; 512 if ((ctrl & LHB_LINKCTRL_ERRORS) != 0 && !linkerr) { 513 if (_pciverbose > PCI_FLG_NORMAL) 514 pci_tagprintf(SB1250_LDT_BRIDGE, 515 "LDT Err, count %d Err = 0x%04x\n", 516 count, ctrl & 0xffff); 517 linkerr = 1; 518 } 519 if (count == maxpoll) { 520 if (_pciverbose > PCI_FLG_NORMAL) 521 pci_tagprintf(SB1250_LDT_BRIDGE, "Link timeout\n"); 522 linkerr = 1; 523 } 524 } 525 526 if (_pciverbose > PCI_FLG_NORMAL) 527 pci_tagprintf(SB1250_LDT_BRIDGE, "lhb_link_ready: count %d\n", count); 528 return linkerr; 529} 530 531static void 532lhb_null_config (void) 533{ 534 /* Even if the LDT fabric is not to be initialized by us, we must 535 write the bus number, base and limit registers in the host 536 bridge for proper operation (see 8.11.1) */ 537 pcireg_t iodata; 538 pcireg_t memdata; 539 540 /* The primary bus is 0. Set secondary, subordinate to 0 also. */ 541 pci_conf_write32(SB1250_LDT_BRIDGE, PPB_BUSINFO_REG, 0); 542 543 iodata = pci_conf_read32(SB1250_LDT_BRIDGE, PPB_IO_STATUS_REG); 544 iodata &=~ (PPB_IO_BASE_MASK | PPB_IO_LIMIT_MASK); 545 iodata |= (1 << 4) | (0 << (8+4)); 546 pci_conf_write32(SB1250_LDT_BRIDGE, PPB_IO_STATUS_REG, iodata); 547 iodata = 0x0000f200; /* recommended value */ 548 pci_conf_write32(SB1250_LDT_BRIDGE, PPB_IO_UPPER_REG, iodata); 549 550 memdata = pci_conf_read32(SB1250_LDT_BRIDGE, PPB_MEM_REG); 551 memdata &=~ (PPB_MEM_BASE_MASK | PPB_MEM_LIMIT_MASK); 552 memdata |= (1 << 4) | (0 << (16+4)); /* empty window */ 553 pci_conf_write32(SB1250_LDT_BRIDGE, PPB_MEM_REG, memdata); 554} 555 556 557/* 558 * LDT host bridge initialization. 559 */ 560static void 561lhb_init (int rev017, unsigned linkfreq, unsigned buffctl) 562{ 563 int i; 564 pcireg_t cr; 565 pcireg_t sri_cmd; 566 volatile pcireg_t t; /* used for reads that push writes */ 567 uint8_t ldt_freq; 568 int linkerr; 569 int retry; 570 571 sb1250_ldt_init = 0; 572 573 /* Clear any pending error bits */ 574 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG); 575 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG, t | LHB_ERR_STATUS); 576 577 cr = pci_conf_read32(SB1250_LDT_BRIDGE, PCI_CLASS_REG); 578 eoi_implemented = (PCI_REVISION(cr) >= 2); 579 580 /* First set up System Reset Initialization registers (Table 581 8-12). This code is designed to be run following a full reset. 582 After a chip warm reset (SipReady already set), most of it is 583 skipped. Depending on previous history, that can leave things 584 in an inconsistent state, but there's no recovery from that 585 short of a chip cold reset. */ 586 587 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_SRI_CMD_REG); 588 if (t & LHB_SRI_CMD_SIPREADY) { 589 pci_tagprintf(SB1250_LDT_BRIDGE, "Warning: SipReady already set\n"); 590 /* Try just doing a warm reset. */ 591 lhb_link_reset(CFE_HZ/10); 592 goto finish; 593 } 594 595 if (rev017) { 596 /* LDT 0.17 compatibility mode: 597 SriCmd = (!LinkFreqDirect, LdtPLLCompat, [DisStarveCnt,] 598 TxInitialOffset=5, 599 RxMargin=2, 600 !SipReady) 601 */ 602 sri_cmd = LHB_SRI_CMD_PLLCOMPAT; 603 } else { 604 /* LDT 1.0x partial compatibility mode: 605 SriCmd = (!LinkFreqDirect, !LdtPLLCompat, [DisStarveCnt,] 606 TxInitialOffset=5, 607 RxMargin=2, 608 !SipReady) 609 */ 610 sri_cmd = 0; 611 } 612 613 /* Empirically, RxMargin is not critical with a 200 MHz LDT clock 614 but must be small (less than 15, and 0 seems reliable) with a 615 400 MHz LDT clock. Current default is 2. */ 616 sri_cmd |= ((2 << LHB_SRI_CMD_RXMARGIN_SHIFT) | 617 (5 << LHB_SRI_CMD_TXOFFSET_SHIFT) | 618 0x1010); /* Rx/TxDen defaults */ 619 620 /* Setting DisStarveCnt is recommended for Pass 1 parts. */ 621 if (PCI_REVISION(cr) == 1) 622 sri_cmd |= LHB_SRI_CMD_DISSTARVATIONCNT; 623 624 /* Map the link frequency to a supported value. Note: we assume 625 that the CPU and IOB0 clocks are set high enough for the 626 selected frequency. In LDT 0.17 compatibility mode, this is 627 the final frequency. In LDT 1.0x partial compatibility mode, 628 this becomes the target frequency for link sizing. */ 629 if (linkfreq < 200) 630 linkfreq = 200; 631 else if (linkfreq > 800) 632 linkfreq = 800; 633 /* Passes 1 and 2 do not support LINKFREQDIRECT. Force a standard value. */ 634 linkfreq = ((linkfreq + (50-1))/100) * 100; 635 if (linkfreq == 700) linkfreq = 600; /* No code point */ 636 if (rev017) 637 xprintf("HyperTransport: %d MHz\n", linkfreq); 638 639 if (linkfreq % 100 == 0 && linkfreq != 700) { 640 /* Encode supported standard values per the LDT spec. */ 641 switch (linkfreq) { 642 default: 643 case 200: ldt_freq = LHB_LFREQ_200; break; 644 case 300: ldt_freq = LHB_LFREQ_300; break; 645 case 400: ldt_freq = LHB_LFREQ_400; break; 646 case 500: ldt_freq = LHB_LFREQ_500; break; 647 case 600: ldt_freq = LHB_LFREQ_600; break; 648 case 800: ldt_freq = LHB_LFREQ_800; break; 649 } 650 } else { 651 /* Compute PLL ratio for 100 MHz reference in 3b1 format (Table 23) */ 652 sri_cmd |= LHB_SRI_CMD_LINKFREQDIRECT; 653 ldt_freq = linkfreq / 50; 654 } 655 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_SRI_CMD_REG, sri_cmd); 656 657 /* Set the SRI dividers */ 658 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_SRI_TXNUM_REG, 0x0000ffff); 659 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_SRI_RXNUM_REG, 0x0000ffff); 660 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_SRI_RXNUM_REG); /* push */ 661 662 /* Directed test: SPIN(10) here */ 663 for (i = 0; i < 10; i++) 664 t = pci_conf_read32(SB1250_LDT_BRIDGE, PCI_ID_REG); 665 666 667 if (rev017) { 668 if (ldt_freq == LHB_LFREQ_200) { 669 pci_conf_write8(SB1250_LDT_BRIDGE, LHB_LFREQ_REG, LHB_LFREQ_400); 670 t = pci_conf_read8(SB1250_LDT_BRIDGE, LHB_LFREQ_REG); 671 cfe_sleep (CFE_HZ/2); 672 } 673 pci_conf_write8(SB1250_LDT_BRIDGE, LHB_LFREQ_REG, ldt_freq); 674 } else { 675 pci_conf_write8(SB1250_LDT_BRIDGE, LHB_LFREQ_REG, LHB_LFREQ_400); 676 t = pci_conf_read8(SB1250_LDT_BRIDGE, LHB_LFREQ_REG); 677 cfe_sleep (CFE_HZ/2); 678 pci_conf_write8(SB1250_LDT_BRIDGE, LHB_LFREQ_REG, LHB_LFREQ_200); 679 } 680 681 /* Set the Error Control register (some fatal interrupts). */ 682 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG, 0x00001209); 683 684 /* Set the SRI Xmit Control register. */ 685 pci_conf_write32(SB1250_LDT_BRIDGE, 686 LHB_SRI_CTRL_REG, 0x00040000 | buffctl); 687 if (_pciverbose > PCI_FLG_NORMAL) 688 pci_tagprintf(SB1250_LDT_BRIDGE, "BuffCtl = 0x%08x\n", 689 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_SRI_CTRL_REG)); 690 691 /* Set the Tx buffer size (16 buffers each). */ 692 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_TXBUFCNT_REG, 0x00ffffff); 693 694 /* Push the writes */ 695 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_TXBUFCNT_REG); /* push */ 696 697 /* Indicate SIP Ready */ 698 sri_cmd |= LHB_SRI_CMD_SIPREADY; 699 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_SRI_CMD_REG, sri_cmd); 700 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_SRI_CMD_REG); /* push */ 701 702 retry = (sb1250_ldt_slave_mode ? 4 : 1); 703 for (;;) { 704 /* wait for LinkFail or InitDone */ 705 linkerr = lhb_link_ready(1<<20); /* empirical delay */ 706 707 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG); 708 if ((t & LHB_ERR_STATUS) != 0) { 709 linkerr = 1; 710 if (_pciverbose > PCI_FLG_NORMAL) 711 pci_tagprintf(SB1250_LDT_BRIDGE, 712 "ErrStat = 0x%02x\n", t >> 24); 713 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG, 714 t | LHB_ERR_STATUS); 715 } 716 717 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG); 718 if ((t & LHB_LINKCTRL_ERRORS) != 0) { 719 linkerr = 1; 720 if (_pciverbose > PCI_FLG_NORMAL) 721 pci_tagprintf(SB1250_LDT_BRIDGE, 722 "LinkCtrl CRCErr = 0x%01x\n", (t >> 8) & 0xf); 723 } 724 725 if (!linkerr || retry == 0) 726 break; 727 728 /* Clear errors in preparation for another try. Delay long 729 enough (below) for CRC errors to reappear; otherwise, the 730 link can look good, but subsequent non-posted transactions 731 will hang. */ 732 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG); 733 t |= LDT_LINKCTRL_CRCERROR_MASK; /* Clear CrcErr bits */ 734 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG, t); 735 736 /* Try again. Do a reset iff an LDT master, since a poorly 737 timed reset by a slave will break any link initialization 738 in progress. */ 739 retry--; 740 741 if (sb1250_ldt_slave_mode) 742 cfe_sleep(CFE_HZ/10); 743 else 744 lhb_link_reset(CFE_HZ/10); 745 } 746 747 /* Rev 0.17 does not support dyanmic frequency updates. */ 748 if (!rev017) { 749 /* Leave the target frequency in the LinkFreq register, which is 750 just a shadow until a link reset happens. */ 751 pci_conf_write8(SB1250_LDT_BRIDGE, LHB_LFREQ_REG, ldt_freq); 752 } 753 754 finish: 755 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG); 756 757 if ((t & LDT_LINKCTRL_INITDONE) == 0) { 758 xprintf("HyperTransport not initialized: InitDone not set\n"); 759 if (_pciverbose > PCI_FLG_NORMAL) 760 pci_tagprintf(SB1250_LDT_BRIDGE, 761 " Link Cmd = 0x%08x, Link Ctrl = 0x%08x\n", 762 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCMD_REG), 763 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG)); 764 } else if ((t & LHB_LINKCTRL_ERRORS) != 0) { 765 xprintf("HyperTransport not initialized: " 766 "LinkFail or CRCErr set, LinkCtrl = 0x%08x\n", t); 767 } else if (!sb1250_ldt_slave_mode) 768 sb1250_ldt_init = 1; 769 770 /* Clear any pending error bits */ 771 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG); 772 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG, t & 0xff000000); 773 774 if (sb1250_ldt_slave_mode) { 775 /* This is LDT slave mode. The documentation is not very clear 776 on how much low level initialization should be done before 777 sleeping. We just set Master Enable so that we can subsequently 778 access LDT space. */ 779 pcireg_t cmd; 780 781 /* If there are intermediate devices on the LDT, we would like 782 our addressing to match the master's, but we don't know it 783 and can't force it here. Instead, we close all the windows 784 into configurable space, which is at least safe. */ 785 lhb_null_config(); 786 787 cmd = pci_conf_read32(SB1250_LDT_BRIDGE, PCI_COMMAND_STATUS_REG); 788 cmd &= (PCI_COMMAND_MASK << PCI_COMMAND_SHIFT); /* preserve status */ 789 cmd |= PCI_COMMAND_MASTER_ENABLE; 790 pci_conf_write32(SB1250_LDT_BRIDGE, PCI_COMMAND_STATUS_REG, cmd); 791 } else if (!sb1250_ldt_init) { 792 pcireg_t lr; 793 794 lhb_null_config(); 795 796 /* Also, terminate the link */ 797 lr = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG); 798 lr |= LDT_LINKCTRL_EOC; 799 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG, lr); 800 lr |= LDT_LINKCTRL_TXOFF; 801 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG, lr); 802 } 803 804 show_ldt_status(); 805} 806 807 808/* 809 * Called to initialise IOB0 and the host bridges at the beginning of time. 810 */ 811int 812pci_hwinit (int port, pci_flags_t flags) 813{ 814 int i; 815 int rev017; 816 unsigned linkfreq, buffctl; 817 uint64_t syscfg; 818 const char *str; 819 820 /* define the address spaces and capabilities */ 821 822 if (port != 0) 823 return -1; 824 pci_set_root(); 825 826 /* initialise global data */ 827 828 syscfg = SBREADCSR(A_SCD_SYSTEM_CFG); 829 sb1250_in_device_mode = ((syscfg & M_SYS_PCI_HOST) == 0); 830 if (cfe_startflags & CFE_LDT_SLAVE) 831 sb1250_ldt_slave_mode = 1; 832 else 833 sb1250_ldt_slave_mode = 0; 834 835 eoi_implemented = 0; /* conservative default */ 836 837 /* Check for any relevant environment variables. */ 838 rev017 = ((flags & PCI_FLG_LDT_REV_017) != 0); 839 840 /* Choose the LDT link frequency. [C]SWARM boards are now set for 841 400 MHz by default */ 842 str = env_getenv("LDT_LINKFREQ"); 843 linkfreq = (str ? atoi(str) : 400); 844 845 /* Choose the buffer allocation (favor posted writes by default) */ 846 str = env_getenv("LDT_BUFFERS"); 847 buffctl = (str ? atoi(str) & 0xFFFF : 0x2525); 848 849 _pci_bus[_pci_nbus] = sb1250_pci_bus; 850 _pci_bus[_pci_nbus].port = port; 851 _pci_nbus++; 852 for (i = _pci_nbus; i < MAXBUS; i++) 853 _pci_bus[i] = secondary_pci_bus; 854 855 /* stop the SB-1250 from servicing any further PCI or LDT requests */ 856 pci_conf_write32(SB1250_PCI_BRIDGE, PCI_COMMAND_STATUS_REG, 0); 857 pci_conf_write32(SB1250_LDT_BRIDGE, PCI_COMMAND_STATUS_REG, 0); 858 859 /* initialize the PCI host bridge */ 860 phb_init(); 861 862 /* initialize the LDT host bridge */ 863 lhb_init(rev017, linkfreq, buffctl); 864 865 cfe_sleep(CFE_HZ); /* add some delay */ 866 867 return 0; 868} 869 870/* 871 * Called to update the host bridge after we've scanned each PCI device 872 * and know what is possible. 873 */ 874void 875pci_hwreinit (int port, pci_flags_t flags) 876{ 877 pcireg_t cmd; 878 879 /* note: this is not officially supported by sb1250, perhaps no effect! */ 880 if (_pci_bus[0].fast_b2b) { 881 /* fast back-to-back is supported by all devices */ 882 cmd = pci_conf_read32(SB1250_PCI_BRIDGE, PCI_COMMAND_STATUS_REG); 883 cmd &= (PCI_COMMAND_MASK << PCI_COMMAND_SHIFT); /* preserve status */ 884 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 885 pci_conf_write32(SB1250_PCI_BRIDGE, PCI_COMMAND_STATUS_REG, cmd); 886 } 887 888 /* Latency timer, cache line size set by pci_setup_devices (pciconf.c) */ 889 890 /* enable PCI read/write error interrupts */ 891} 892 893 894/* The following functions provide for device-specific setup required 895 during configuration. There is nothing SiByte-specific about them, 896 and it would be better to do the packaging and registration in a 897 more modular way. */ 898 899#define PCI_VENDOR_API 0x14d9 900#define PCI_PRODUCT_API_STURGEON 0x0010 901extern void sturgeon_setup(pcitag_t tag, pci_flags_t flags); 902 903#define PCI_VENDOR_AMD 0x1022 904#define PCI_PRODUCT_PLX_HT7520 0x7450 905#define PCI_PRODUCT_PLX_HT7520_APIC 0x7451 906extern void ht7520apic_preset(pcitag_t tag); 907extern void ht7520apic_setup(pcitag_t tag); 908 909#define PCI_PRODUCT_AMD_8151 0x7454 910 911/* Dispatch functions for device pre- and post-configuration hooks. */ 912 913/* Called for each function prior to assigning PCI resources. */ 914int 915pci_device_preset (pcitag_t tag) 916{ 917 pcireg_t id; 918 int skip; 919 920 skip = 0; 921 id = pci_conf_read(tag, PCI_ID_REG); 922 switch (PCI_VENDOR(id)) { 923 case PCI_VENDOR_SIBYTE: 924 /* Check for a host bridge seen internally, in which case 925 we don't want to allocate any address space for its 926 BARs. */ 927 if (tag == SB1250_PCI_BRIDGE) 928 skip = 1; 929 break; 930 case PCI_VENDOR_AMD: 931 switch (PCI_PRODUCT(id)) { 932 case PCI_PRODUCT_PLX_HT7520_APIC: 933 ht7520apic_preset (tag); 934 break; 935 case PCI_PRODUCT_AMD_8151: 936 skip = 1; 937 break; 938 default: 939 break; 940 } 941 break; 942 default: 943 break; 944 } 945 return skip; 946} 947 948 949void 950pci_device_setup (pcitag_t tag) 951{ 952 pcireg_t id = pci_conf_read(tag, PCI_ID_REG); 953 954 switch (PCI_VENDOR(id)) { 955 case PCI_VENDOR_AMD: 956 if (PCI_PRODUCT(id) == PCI_PRODUCT_PLX_HT7520_APIC) 957 ht7520apic_setup (tag); 958 break; 959 default: 960 break; 961 } 962} 963 964/* Called for each bridge (Type 1) function after configuring the 965 secondary bus, to allow device-specific initialization. */ 966void 967pci_bridge_setup (pcitag_t tag, pci_flags_t flags) 968{ 969 pcireg_t id = pci_conf_read(tag, PCI_ID_REG); 970 971 switch (PCI_VENDOR(id)) { 972 case PCI_VENDOR_API: 973 if (PCI_PRODUCT(id) == PCI_PRODUCT_API_STURGEON) 974 sturgeon_setup (tag, flags); 975 break; 976 case PCI_VENDOR_AMD: 977 /* The PLX ht7520 requires configuration of the 978 interrupt mapping, but it packages the IOAPIC as a 979 separate function, registers of which will not yet have 980 been initialized if the standard traversal order is 981 followed. See previous. */ 982 break; 983 default: 984 break; 985 } 986} 987 988 989/* Machine dependent access primitives and utility functions */ 990 991void 992pci_flush (void) 993{ 994 /* note: this is a noop for the SB-1250. */ 995} 996 997 998pcitag_t 999pci_make_tag (int port, int bus, int device, int function) 1000{ 1001 return SB1250_PCI_MAKE_TAG(bus, device, function); 1002} 1003 1004void 1005pci_break_tag (pcitag_t tag, 1006 int *portp, int *busp, int *devicep, int *functionp) 1007{ 1008 if (portp) *portp = (tag >> 24) & PCI_PORTMAX; 1009 if (busp) *busp = (tag >> 16) & PCI_BUSMAX; 1010 if (devicep) *devicep = (tag >> 11) & PCI_DEVMAX; 1011 if (functionp) *functionp = (tag >> 8) & PCI_FUNCMAX; 1012} 1013 1014 1015int 1016pci_canscan (pcitag_t tag) 1017{ 1018 int port, bus, device, function; 1019 1020 pci_break_tag (tag, &port, &bus, &device, &function); 1021 1022 if (port > PCI_PORTMAX 1023 || bus > PCI_BUSMAX || device > PCI_DEVMAX || function > PCI_FUNCMAX) 1024 return 0; 1025 1026 if (bus == 0) { 1027 if (sb1250_in_device_mode) { 1028 /* Scan the LDT chain, but only the LDT host bridge on PCI. */ 1029 if (device != 1) 1030 return 0; 1031 } 1032 if (sb1250_ldt_slave_mode || !sb1250_ldt_init) { 1033 /* Scan the PCI devices but not the LDT chain. */ 1034 if (device == 1) 1035 return 0; 1036 } 1037 if (device > 20) { 1038 /* Chip bug: asserts IDSEL for device 20 for all devices > 20. */ 1039 return 0; 1040 } 1041 } 1042 1043 return 1; 1044} 1045 1046int 1047pci_probe_tag(pcitag_t tag) 1048{ 1049 physaddr_t addrp; 1050 pcireg_t data; 1051 1052 if (!pci_canscan(tag)) 1053 return 0; 1054 1055 addrp = (physaddr_t) SB1250_CFG_ADDR(tag, PCI_ID_REG, 4); 1056 1057 /* An earlier version of this code cleared the MasterAbort and 1058 TargetAbort bits in the PCI host bridge, did the read, and 1059 looked for those bits to be set. For the SB-1250, that's 1060 inappropriate because 1061 - it's the wrong host bridge for devices behind LDT. 1062 - PCI host bridge registers aren't readable in Device mode. 1063 - it loses status if testing the PCI host bridge itself. 1064 We rely on getting 0xffff when reading the vendor ID. Note 1065 that this still has side effects on the host bridge registers. 1066 */ 1067 1068 data = phys_read32(addrp); /* device + vendor ID */ 1069 mips_wbflush(); 1070 1071 /* if it returned all vendor id bits set, it's not a device */ 1072 return (PCI_VENDOR(data) != 0xffff); 1073} 1074 1075 1076/* Read/write access to PCI configuration registers. For most 1077 applications, pci_conf_read<N> and pci_conf_write<N> are deprecated 1078 unless N = 32. */ 1079 1080static pcireg_t 1081pci_conf_readn(pcitag_t tag, int reg, int width) 1082{ 1083 physaddr_t addrp; 1084 pcireg_t data; 1085#if PCI_DEBUG != 0 1086 int port, bus, device, function; 1087 1088 if (reg & (width-1) || reg < 0 || reg >= PCI_REGMAX) { 1089 if (_pciverbose != 0) 1090 pci_tagprintf(tag, "pci_conf_readn: bad reg 0x%x\n", reg); 1091 return 0; 1092 } 1093 1094 pci_break_tag(tag, &port, &bus, &device, &function); 1095 if (bus > PCI_BUSMAX || device > PCI_DEVMAX || function > PCI_FUNCMAX) { 1096 if (_pciverbose != 0) 1097 pci_tagprintf(tag, "pci_conf_readn: bad tag 0x%x\n", tag); 1098 return 0; 1099 } 1100#endif /* PCI_DEBUG */ 1101 1102 mips_wbflush(); 1103 1104 addrp = (physaddr_t) SB1250_CFG_ADDR(tag, reg, width); 1105 switch (width) { 1106 case 1: 1107 data = (pcireg_t) phys_read8(addrp); 1108 break; 1109 case 2: 1110 data = (pcireg_t) phys_read16(addrp); 1111 break; 1112 default: 1113 case 4: 1114 data = (pcireg_t) phys_read32(addrp); 1115 break; 1116 } 1117 1118 mips_wbflush(); 1119 1120 return data; 1121} 1122 1123pcireg_t 1124pci_conf_read8(pcitag_t tag, int reg) 1125{ 1126 return pci_conf_readn(tag, reg, 1); 1127} 1128 1129pcireg_t 1130pci_conf_read16(pcitag_t tag, int reg) 1131{ 1132 return pci_conf_readn(tag, reg, 2); 1133} 1134 1135pcireg_t 1136pci_conf_read(pcitag_t tag, int reg) 1137{ 1138 return pci_conf_readn(tag, reg, 4); 1139} 1140 1141static void 1142pci_conf_writen(pcitag_t tag, int reg, pcireg_t data, int width) 1143{ 1144 physaddr_t addrp; 1145#if PCI_DEBUG != 0 1146 int port, bus, device, function; 1147 1148 if (reg & (width-1) || reg < 0 || reg > PCI_REGMAX) { 1149 if (_pciverbose != 0) 1150 pci_tagprintf(tag, "pci_conf_writen: bad reg 0x%x\n", reg); 1151 return; 1152 } 1153 1154 pci_break_tag(tag, &port, &bus, &device, &function); 1155 if (bus > PCI_BUSMAX || device > PCI_DEVMAX || function > PCI_FUNCMAX) { 1156 if (_pciverbose != 0) 1157 pci_tagprintf(tag, "pci_conf_writen: bad tag 0x%x\n", tag); 1158 return; 1159 } 1160#endif /* PCI_DEBUG */ 1161 1162 mips_wbflush(); 1163 1164 addrp = (physaddr_t) SB1250_CFG_ADDR(tag, reg, width); 1165 switch (width) { 1166 case 1: 1167 phys_write8(addrp, data); 1168 break; 1169 case 2: 1170 phys_write16(addrp, data); 1171 break; 1172 default: 1173 case 4: 1174 phys_write32(addrp, data); 1175 break; 1176 } 1177 1178 mips_wbflush(); 1179} 1180 1181void 1182pci_conf_write8(pcitag_t tag, int reg, pcireg_t data) 1183{ 1184 pci_conf_writen(tag, reg, data, 1); 1185} 1186 1187void 1188pci_conf_write16(pcitag_t tag, int reg, pcireg_t data) 1189{ 1190 pci_conf_writen(tag, reg, data, 2); 1191} 1192 1193void 1194pci_conf_write(pcitag_t tag, int reg, pcireg_t data) 1195{ 1196 pci_conf_writen(tag, reg, data, 4); 1197} 1198 1199/* Acked writes are intended primarily for updating the unitID field 1200 during HT fabric initialization. The write changes the address of 1201 the target, so further accesses should be avoided until the write 1202 completes or times out. */ 1203int 1204pci_conf_write_acked(pcitag_t tag, int reg, pcireg_t data) 1205{ 1206 int done; 1207 1208 if (sb1250_ldt_init) { 1209 int port, bus; 1210 pcireg_t bus_info, cr; 1211 int i; 1212 1213 pci_break_tag(tag, &port, &bus, NULL, NULL); 1214 bus_info = pci_conf_read(SB1250_LDT_BRIDGE, PPB_BUSINFO_REG); 1215 1216 if (bus >= PPB_BUSINFO_SECONDARY(bus_info) 1217 && bus <= PPB_BUSINFO_SUBORD(bus_info)) { 1218 1219 /* Write through the LDT host bridge. An HT configuration 1220 write is non-posted, but the ZBbus write completes as 1221 if it were posted. The following code assumes there 1222 are no overlapping non-posted HT writes. */ 1223 1224 cr = pci_conf_read(SB1250_LDT_BRIDGE, PCI_CLASS_REG); 1225 if (PCI_REVISION(cr) >= 2) { 1226 /* Current parts can count tgt_done responses. */ 1227 unsigned int count, prev_count; 1228 1229 prev_count = pci_conf_read(SB1250_LDT_BRIDGE, LHB_ASTAT_REG); 1230 prev_count &= LHB_ASTAT_TGTDONE_MASK; 1231 1232 pci_conf_write(tag, reg, data); 1233 1234 for (i = 0; i < 1000; i++) { 1235 count = pci_conf_read(SB1250_LDT_BRIDGE, LHB_ASTAT_REG); 1236 count &= LHB_ASTAT_TGTDONE_MASK; 1237 if (count != prev_count) 1238 break; 1239 } 1240 done = (count != prev_count); 1241 } else { 1242 /* For pass 1, a couple of innocuous writes seems the 1243 best we can do (a read with the new tag could hang) */ 1244 pci_conf_write(tag, reg, data); 1245 for (i = 0; i < 10; i++) 1246 pci_conf_write(tag, PCI_ID_REG, 0); 1247 done = 1; 1248 } 1249 } else { 1250 /* Write through the PCI host bridge. Just read it back. */ 1251 1252 pci_conf_write(tag, reg, data); 1253 (void) pci_conf_read(tag, reg); /* Push the write */ 1254 done = 1; 1255 } 1256 } else { 1257 /* No LDT. Write and read back. */ 1258 1259 pci_conf_write(tag, reg, data); 1260 (void) pci_conf_read(tag, reg); 1261 done = 1; 1262 } 1263 return done; 1264} 1265 1266 1267 1268int 1269pci_map_io(pcitag_t tag, int reg, pci_endian_t endian, phys_addr_t *pap) 1270{ 1271 pcireg_t address; 1272 phys_addr_t pa; 1273 1274 if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) { 1275 if (_pciverbose != 0) 1276 pci_tagprintf(tag, "pci_map_io: bad request\n"); 1277 return -1; 1278 } 1279 1280 address = pci_conf_read(tag, reg); 1281 1282 if ((address & PCI_MAPREG_TYPE_IO) == 0) { 1283 if (_pciverbose != 0) 1284 pci_tagprintf(tag, "pci_map_io: attempt to i/o map a memory region\n"); 1285 return -1; 1286 } 1287 1288 pa = ((address & PCI_MAPREG_IO_ADDR_MASK) - Q.pci_io_base) + Q.io_space; 1289 if (endian == PCI_MATCH_BITS) 1290 pa |= Q.io_bit_endian; 1291 *pap = pa; 1292 return 0; 1293} 1294 1295int 1296pci_map_mem(pcitag_t tag, int reg, pci_endian_t endian, phys_addr_t *pap) 1297{ 1298 pcireg_t address; 1299 phys_addr_t pa; 1300 1301 if (reg == PCI_MAPREG_ROM) { 1302 /* expansion ROM */ 1303 address = pci_conf_read(tag, reg); 1304 if ((address & PCI_MAPREG_ROM_ENABLE) == 0) { 1305 pci_tagprintf(tag, "pci_map_mem: attempt to map missing rom\n"); 1306 return -1; 1307 } 1308 pa = address & PCI_MAPREG_ROM_ADDR_MASK; 1309 } else { 1310 if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) { 1311 if (_pciverbose != 0) 1312 pci_tagprintf(tag, "pci_map_mem: bad request\n"); 1313 return -1; 1314 } 1315 1316 address = pci_conf_read(tag, reg); 1317 1318 if ((address & PCI_MAPREG_TYPE_IO) != 0) { 1319 if (_pciverbose != 0) 1320 pci_tagprintf(tag, "pci_map_mem: attempt to memory map an I/O region\n"); 1321 return -1; 1322 } 1323 1324 pa = address & PCI_MAPREG_MEM_ADDR_MASK; 1325 1326 switch (address & PCI_MAPREG_MEM_TYPE_MASK) { 1327 case PCI_MAPREG_MEM_TYPE_32BIT: 1328 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1329 break; 1330 case PCI_MAPREG_MEM_TYPE_64BIT: 1331 if (reg + 4 < PCI_MAPREG_END) 1332 pa |= ((phys_addr_t)pci_conf_read(tag, reg+4) << 32); 1333 else { 1334 if (_pciverbose != 0) 1335 pci_tagprintf(tag, "pci_map_mem: bad 64-bit reguest\n"); 1336 return -1; 1337 } 1338 break; 1339 default: 1340 if (_pciverbose != 0) 1341 pci_tagprintf(tag, "pci_map_mem: reserved mapping type\n"); 1342 return -1; 1343 } 1344 } 1345 1346 pa = (pa - Q.pci_mem_base) + Q.mem_space; 1347 if (endian == PCI_MATCH_BITS) 1348 pa |= Q.mem_bit_endian; 1349 *pap = pa; 1350 return 0; 1351} 1352 1353 1354#define ISAPORT_BASE(x) (Q.io_space + (x)) 1355 1356uint8_t 1357inb (unsigned int port) 1358{ 1359 return phys_read8(ISAPORT_BASE(port)); 1360} 1361 1362uint16_t 1363inw (unsigned int port) 1364{ 1365 return phys_read16(ISAPORT_BASE(port)); 1366} 1367 1368uint32_t 1369inl (unsigned int port) 1370{ 1371 return phys_read32(ISAPORT_BASE(port)); 1372} 1373 1374void 1375outb (unsigned int port, uint8_t val) 1376{ 1377 phys_write8(ISAPORT_BASE(port), val); 1378 mips_wbflush(); 1379} 1380 1381void 1382outw (unsigned int port, uint16_t val) 1383{ 1384 phys_write16(ISAPORT_BASE(port), val); 1385 mips_wbflush(); 1386} 1387 1388void 1389outl (unsigned int port, uint32_t val) 1390{ 1391 phys_write32(ISAPORT_BASE(port), val); 1392 mips_wbflush(); 1393} 1394 1395 1396/* Management of MAP table */ 1397 1398int 1399pci_map_window(phys_addr_t pa, 1400 unsigned int offset, unsigned int len, 1401 int l2ca, int endian) 1402{ 1403 unsigned int first, last; 1404 unsigned int i; 1405 uint32_t addr; 1406 uint32_t entry; 1407 1408 if (len == 0) 1409 return 0; 1410 1411 1412 first = offset / PHB_MAP_ENTRY_SPAN; 1413 last = (offset + (len-1)) / PHB_MAP_ENTRY_SPAN; 1414 1415 if (last >= PHB_MAP_N_ENTRIES) 1416 return -1; 1417 1418 addr = (pa / PHB_MAP_ENTRY_SPAN) << PHB_MAP_ADDR_SHIFT; 1419 for (i = first; i <= last; i++) { 1420 entry = (addr & PHB_MAP_ADDR_MASK) | PHB_MAP_ENABLE; 1421 if (l2ca) 1422 entry |= PHB_MAP_L2CA; 1423 if (endian) 1424 entry |= PHB_MAP_ENDIAN; 1425 pci_conf_write32(SB1250_PCI_BRIDGE, PHB_MAP_REG_BASE + 4*i, entry); 1426 addr += (1 << PHB_MAP_ADDR_SHIFT); 1427 } 1428 1429 return 0; 1430} 1431 1432int 1433pci_unmap_window(unsigned int offset, unsigned int len) 1434{ 1435 unsigned int first, last; 1436 unsigned int i; 1437 1438 if (len == 0) 1439 return 0; 1440 1441 1442 first = offset / PHB_MAP_ENTRY_SPAN; 1443 if (first >= PHB_MAP_N_ENTRIES) 1444 return 0; 1445 1446 last = (offset + (len-1)) / PHB_MAP_ENTRY_SPAN; 1447 if (last >= PHB_MAP_N_ENTRIES) 1448 last = PHB_MAP_N_ENTRIES - 1; 1449 1450 for (i = first; i <= last; i++) 1451 pci_conf_write32(SB1250_PCI_BRIDGE, PHB_MAP_REG_BASE + 4*i, 0); 1452 1453 return 0; 1454} 1455 1456 1457/* Map PCI interrupts A, B, C, D into a value for the IntLine 1458 register. For SB1250, return the source number used by the 1459 interrupt mapper, or 0xff if none. */ 1460uint8_t 1461pci_int_line(uint8_t pci_int) 1462{ 1463 return (pci_int == 0) ? 0xff : (56 + (pci_int-1)); 1464} 1465