1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * UART Constants File: sb1250_uart.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the SB1250's UARTs 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 * Author: Mitch Lichtenberg (mpl@broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions 27 * as they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. The "Broadcom Corporation" 31 * name may not be used to endorse or promote products derived 32 * from this software without the prior written permission of 33 * Broadcom Corporation. 34 * 35 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 36 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 37 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 38 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 39 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 40 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 43 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 44 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 45 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 46 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 47 * THE POSSIBILITY OF SUCH DAMAGE. 48 ********************************************************************* */ 49 50 51#ifndef _SB1250_UART_H 52#define _SB1250_UART_H 53 54#include "sb1250_defs.h" 55 56/* ********************************************************************** 57 * DUART Registers 58 ********************************************************************** */ 59 60/* 61 * DUART Mode Register #1 (Table 10-3) 62 * Register: DUART_MODE_REG_1_A 63 * Register: DUART_MODE_REG_1_B 64 */ 65 66#define S_DUART_BITS_PER_CHAR 0 67#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR) 68#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR) 69 70#define K_DUART_BITS_PER_CHAR_RSV0 0 71#define K_DUART_BITS_PER_CHAR_RSV1 1 72#define K_DUART_BITS_PER_CHAR_7 2 73#define K_DUART_BITS_PER_CHAR_8 3 74 75#define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0) 76#define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1) 77#define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7) 78#define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8) 79 80 81#define M_DUART_PARITY_TYPE_EVEN 0x00 82#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) 83 84#define S_DUART_PARITY_MODE 3 85#define M_DUART_PARITY_MODE _SB_MAKEMASK(2,S_DUART_PARITY_MODE) 86#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x,S_DUART_PARITY_MODE) 87 88#define K_DUART_PARITY_MODE_ADD 0 89#define K_DUART_PARITY_MODE_ADD_FIXED 1 90#define K_DUART_PARITY_MODE_NONE 2 91 92#define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD) 93#define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED) 94#define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE) 95 96#define M_DUART_ERR_MODE _SB_MAKEMASK1(5) /* must be zero */ 97 98#define M_DUART_RX_IRQ_SEL_RXRDY 0 99#define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6) 100 101#define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7) 102 103/* 104 * DUART Mode Register #2 (Table 10-4) 105 * Register: DUART_MODE_REG_2_A 106 * Register: DUART_MODE_REG_2_B 107 */ 108 109#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3,0) /* ignored */ 110 111#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) 112#define M_DUART_STOP_BIT_LEN_1 0 113 114#define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4) 115 116 117#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ 118 119#define S_DUART_CHAN_MODE 6 120#define M_DUART_CHAN_MODE _SB_MAKEMASK(2,S_DUART_CHAN_MODE) 121#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x,S_DUART_CHAN_MODE) 122 123#define K_DUART_CHAN_MODE_NORMAL 0 124#define K_DUART_CHAN_MODE_LCL_LOOP 2 125#define K_DUART_CHAN_MODE_REM_LOOP 3 126 127#define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL) 128#define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP) 129#define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP) 130 131/* 132 * DUART Command Register (Table 10-5) 133 * Register: DUART_CMD_A 134 * Register: DUART_CMD_B 135 */ 136 137#define M_DUART_RX_EN _SB_MAKEMASK1(0) 138#define M_DUART_RX_DIS _SB_MAKEMASK1(1) 139#define M_DUART_TX_EN _SB_MAKEMASK1(2) 140#define M_DUART_TX_DIS _SB_MAKEMASK1(3) 141 142#define S_DUART_MISC_CMD 4 143#define M_DUART_MISC_CMD _SB_MAKEMASK(3,S_DUART_MISC_CMD) 144#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x,S_DUART_MISC_CMD) 145 146#define K_DUART_MISC_CMD_NOACTION0 0 147#define K_DUART_MISC_CMD_NOACTION1 1 148#define K_DUART_MISC_CMD_RESET_RX 2 149#define K_DUART_MISC_CMD_RESET_TX 3 150#define K_DUART_MISC_CMD_NOACTION4 4 151#define K_DUART_MISC_CMD_RESET_BREAK_INT 5 152#define K_DUART_MISC_CMD_START_BREAK 6 153#define K_DUART_MISC_CMD_STOP_BREAK 7 154 155#define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0) 156#define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1) 157#define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX) 158#define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX) 159#define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4) 160#define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT) 161#define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) 162#define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) 163 164#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) 165 166/* 167 * DUART Status Register (Table 10-6) 168 * Register: DUART_STATUS_A 169 * Register: DUART_STATUS_B 170 * READ-ONLY 171 */ 172 173#define M_DUART_RX_RDY _SB_MAKEMASK1(0) 174#define M_DUART_RX_FFUL _SB_MAKEMASK1(1) 175#define M_DUART_TX_RDY _SB_MAKEMASK1(2) 176#define M_DUART_TX_EMT _SB_MAKEMASK1(3) 177#define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4) 178#define M_DUART_PARITY_ERR _SB_MAKEMASK1(5) 179#define M_DUART_FRM_ERR _SB_MAKEMASK1(6) 180#define M_DUART_RCVD_BRK _SB_MAKEMASK1(7) 181 182/* 183 * DUART Baud Rate Register (Table 10-7) 184 * Register: DUART_CLK_SEL_A 185 * Register: DUART_CLK_SEL_B 186 */ 187 188#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12,0) 189#define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) 190 191/* 192 * DUART Data Registers (Table 10-8 and 10-9) 193 * Register: DUART_RX_HOLD_A 194 * Register: DUART_RX_HOLD_B 195 * Register: DUART_TX_HOLD_A 196 * Register: DUART_TX_HOLD_B 197 */ 198 199#define M_DUART_RX_DATA _SB_MAKEMASK(8,0) 200#define M_DUART_TX_DATA _SB_MAKEMASK(8,0) 201 202/* 203 * DUART Input Port Register (Table 10-10) 204 * Register: DUART_IN_PORT 205 */ 206 207#define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0) 208#define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1) 209#define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2) 210#define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3) 211#define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4) 212#define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5) 213#define M_DUART_RIN0_PIN _SB_MAKEMASK1(6) 214#define M_DUART_RIN1_PIN _SB_MAKEMASK1(7) 215 216/* 217 * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13) 218 * Register: DUART_INPORT_CHNG 219 */ 220 221#define S_DUART_IN_PIN_VAL 0 222#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL) 223 224#define S_DUART_IN_PIN_CHNG 4 225#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG) 226 227 228/* 229 * DUART Output port control register (Table 10-14) 230 * Register: DUART_OPCR 231 */ 232 233#define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */ 234#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) 235#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ 236#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) 237#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4,4) /* must be zero */ 238 239/* 240 * DUART Aux Control Register (Table 10-15) 241 * Register: DUART_AUX_CTRL 242 */ 243 244#define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0) 245#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) 246#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) 247#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) 248#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4,4) 249 250#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) 251#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) 252 253/* 254 * DUART Interrupt Status Register (Table 10-16) 255 * Register: DUART_ISR 256 */ 257 258#define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) 259#define M_DUART_ISR_RX_A _SB_MAKEMASK1(1) 260#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) 261#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) 262#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) 263#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) 264#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) 265#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) 266 267/* 268 * DUART Channel A Interrupt Status Register (Table 10-17) 269 * DUART Channel B Interrupt Status Register (Table 10-18) 270 * Register: DUART_ISR_A 271 * Register: DUART_ISR_B 272 */ 273 274#define M_DUART_ISR_TX _SB_MAKEMASK1(0) 275#define M_DUART_ISR_RX _SB_MAKEMASK1(1) 276#define M_DUART_ISR_BRK _SB_MAKEMASK1(2) 277#define M_DUART_ISR_IN _SB_MAKEMASK1(3) 278#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) 279 280/* 281 * DUART Interrupt Mask Register (Table 10-19) 282 * Register: DUART_IMR 283 */ 284 285#define M_DUART_IMR_TX_A _SB_MAKEMASK1(0) 286#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) 287#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) 288#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) 289#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4,0) 290 291#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) 292#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) 293#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) 294#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) 295#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4,4) 296 297/* 298 * DUART Channel A Interrupt Mask Register (Table 10-20) 299 * DUART Channel B Interrupt Mask Register (Table 10-21) 300 * Register: DUART_IMR_A 301 * Register: DUART_IMR_B 302 */ 303 304#define M_DUART_IMR_TX _SB_MAKEMASK1(0) 305#define M_DUART_IMR_RX _SB_MAKEMASK1(1) 306#define M_DUART_IMR_BRK _SB_MAKEMASK1(2) 307#define M_DUART_IMR_IN _SB_MAKEMASK1(3) 308#define M_DUART_IMR_ALL _SB_MAKEMASK(4,0) 309#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4,4) 310 311 312/* 313 * DUART Output Port Set Register (Table 10-22) 314 * Register: DUART_SET_OPR 315 */ 316 317#define M_DUART_SET_OPR0 _SB_MAKEMASK1(0) 318#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) 319#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) 320#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) 321#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4,4) 322 323/* 324 * DUART Output Port Clear Register (Table 10-23) 325 * Register: DUART_CLEAR_OPR 326 */ 327 328#define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0) 329#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) 330#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) 331#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) 332#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4,4) 333 334/* 335 * DUART Output Port RTS Register (Table 10-24) 336 * Register: DUART_OUT_PORT 337 */ 338 339#define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0) 340#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) 341#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) 342#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) 343#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4,4) 344 345#define M_DUART_OUT_PIN_SET(chan) \ 346 (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) 347#define M_DUART_OUT_PIN_CLR(chan) \ 348 (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) 349 350#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 351/* 352 * Full Interrupt Control Register 353 */ 354 355#define S_DUART_SIG_FULL _SB_MAKE64(0) 356#define M_DUART_SIG_FULL _SB_MAKEMASK(4,S_DUART_SIG_FULL) 357#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x,S_DUART_SIG_FULL) 358#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL) 359 360#define S_DUART_INT_TIME _SB_MAKE64(4) 361#define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) 362#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) 363#define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) 364#endif /* 1250 PASS2 || 112x PASS1 */ 365 366 367/* ********************************************************************** */ 368 369 370#endif 371