1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * SCD Constants and Macros File: sb1250_scd.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the System Control and Debug module on the 1250. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 * Author: Mitch Lichtenberg (mpl@broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions 27 * as they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. The "Broadcom Corporation" 31 * name may not be used to endorse or promote products derived 32 * from this software without the prior written permission of 33 * Broadcom Corporation. 34 * 35 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 36 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 37 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 38 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 39 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 40 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 43 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 44 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 45 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 46 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 47 * THE POSSIBILITY OF SUCH DAMAGE. 48 ********************************************************************* */ 49 50#ifndef _SB1250_SCD_H 51#define _SB1250_SCD_H 52 53#include "sb1250_defs.h" 54 55/* ********************************************************************* 56 * System control/debug registers 57 ********************************************************************* */ 58 59/* 60 * System Revision Register (Table 4-1) 61 */ 62 63#define M_SYS_RESERVED _SB_MAKEMASK(8,0) 64 65#define S_SYS_REVISION _SB_MAKE64(8) 66#define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) 67#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) 68#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) 69 70#if SIBYTE_HDR_FEATURE_CHIP(1250) 71#define K_SYS_REVISION_BCM1250_PASS1 1 72#define K_SYS_REVISION_BCM1250_PASS2 3 73#define K_SYS_REVISION_BCM1250_A10 11 74#define K_SYS_REVISION_BCM1250_PASS2_2 16 75#define K_SYS_REVISION_BCM1250_B2 17 76#define K_SYS_REVISION_BCM1250_PASS3 32 77 78#define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 79#define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 80#define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 81#define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 82#endif /* 1250 */ 83 84#if SIBYTE_HDR_FEATURE_CHIP(112x) 85#define K_SYS_REVISION_BCM112x_A1 32 86#define K_SYS_REVISION_BCM112x_A2 33 87#endif /* 112x */ 88 89#define S_SYS_PART _SB_MAKE64(16) 90#define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) 91#define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) 92#define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) 93 94#define K_SYS_PART_SB1250 0x1250 95#define K_SYS_PART_BCM1120 0x1121 96#define K_SYS_PART_BCM1125 0x1123 97#define K_SYS_PART_BCM1125H 0x1124 98 99/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ 100#define S_SYS_SOC_TYPE _SB_MAKE64(16) 101#define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) 102#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) 103#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) 104 105#define K_SYS_SOC_TYPE_BCM1250 0x0 106#define K_SYS_SOC_TYPE_BCM1120 0x1 107#define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ 108#define K_SYS_SOC_TYPE_BCM1125 0x3 109#define K_SYS_SOC_TYPE_BCM1125H 0x4 110#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ 111 112/* 113 * Calculate correct SOC type given a copy of system revision register. 114 * 115 * (For the assembler version, sysrev and dest may be the same register. 116 * Also, it clobbers AT.) 117 */ 118#ifdef __ASSEMBLER__ 119#define SYS_SOC_TYPE(dest, sysrev) \ 120 .set push ; \ 121 .set reorder ; \ 122 dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ 123 andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ 124 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ 125 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ 126 b 992f ; \ 127991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \ 128992: \ 129 .set pop 130#else 131#define SYS_SOC_TYPE(sysrev) \ 132 ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ 133 || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ 134 ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) 135#endif 136 137#define S_SYS_WID _SB_MAKE64(32) 138#define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) 139#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) 140#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) 141 142/* System Manufacturing Register 143* Register: SCD_SYSTEM_MANUF 144*/ 145 146/* Wafer ID: bits 31:0 */ 147#define S_SYS_WAFERID1_200 _SB_MAKE64(0) 148#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) 149#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) 150#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) 151 152#define S_SYS_BIN _SB_MAKE64(32) 153#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) 154#define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN) 155#define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) 156 157/* Wafer ID: bits 39:36 */ 158#define S_SYS_WAFERID2_200 _SB_MAKE64(36) 159#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) 160#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) 161#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) 162 163/* Wafer ID: bits 39:0 */ 164#define S_SYS_WAFERID_300 _SB_MAKE64(0) 165#define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) 166#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) 167#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) 168 169#define S_SYS_XPOS _SB_MAKE64(46) 170#define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) 171#define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) 172#define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) 173 174#define S_SYS_YPOS _SB_MAKE64(40) 175#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) 176#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) 177#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) 178 179/* 180 * System Config Register (Table 4-2) 181 * Register: SCD_SYSTEM_CFG 182 */ 183 184#define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) 185#define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) 186#define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) 187#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) 188 189#define S_SYS_PLL_DIV _SB_MAKE64(7) 190#define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) 191#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) 192#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) 193 194#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) 195#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) 196#define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) 197#define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) 198#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 199 200#define S_SYS_BOOT_MODE _SB_MAKE64(17) 201#define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) 202#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) 203#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) 204#define K_SYS_BOOT_MODE_ROM32 0 205#define K_SYS_BOOT_MODE_ROM8 1 206#define K_SYS_BOOT_MODE_SMBUS_SMALL 2 207#define K_SYS_BOOT_MODE_SMBUS_BIG 3 208 209#define M_SYS_PCI_HOST _SB_MAKEMASK1(19) 210#define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) 211#define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) 212#define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) 213#define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) 214#define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) 215#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) 216 217#define S_SYS_CONFIG 26 218#define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) 219#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) 220#define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) 221 222/* The following bits are writeable by JTAG only. */ 223 224#define M_SYS_CLKSTOP _SB_MAKEMASK1(32) 225#define M_SYS_CLKSTEP _SB_MAKEMASK1(33) 226 227#define S_SYS_CLKCOUNT 34 228#define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) 229#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) 230#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) 231 232#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) 233 234#define S_SYS_PLL_IREF 43 235#define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) 236 237#define S_SYS_PLL_VCO 45 238#define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) 239 240#define S_SYS_PLL_VREG 47 241#define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) 242 243#define M_SYS_MEM_RESET _SB_MAKEMASK1(49) 244#define M_SYS_L2C_RESET _SB_MAKEMASK1(50) 245#define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) 246#define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) 247#define M_SYS_SCD_RESET _SB_MAKEMASK1(53) 248 249/* End of bits writable by JTAG only. */ 250 251#define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) 252#define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) 253 254#define M_SYS_UNICPU0 _SB_MAKEMASK1(56) 255#define M_SYS_UNICPU1 _SB_MAKEMASK1(57) 256 257#define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) 258#define M_SYS_EXT_RESET _SB_MAKEMASK1(59) 259#define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) 260 261#define M_SYS_MISR_MODE _SB_MAKEMASK1(61) 262#define M_SYS_MISR_RESET _SB_MAKEMASK1(62) 263 264#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 265#define M_SYS_SW_FLAG _SB_MAKEMASK1(63) 266#endif /* 1250 PASS2 || 112x PASS1 */ 267 268 269/* 270 * Mailbox Registers (Table 4-3) 271 * Registers: SCD_MBOX_CPU_x 272 */ 273 274#define S_MBOX_INT_3 0 275#define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) 276#define S_MBOX_INT_2 16 277#define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) 278#define S_MBOX_INT_1 32 279#define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) 280#define S_MBOX_INT_0 48 281#define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) 282 283/* 284 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) 285 * Registers: SCD_WDOG_INIT_CNT_x 286 */ 287 288#define V_SCD_WDOG_FREQ 1000000 289 290#define S_SCD_WDOG_INIT 0 291#define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) 292 293#define S_SCD_WDOG_CNT 0 294#define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) 295 296#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) 297 298/* 299 * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) 300 */ 301 302#define V_SCD_TIMER_FREQ 1000000 303 304#define S_SCD_TIMER_INIT 0 305#define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT) 306#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 307#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 308 309#define S_SCD_TIMER_CNT 0 310#define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT) 311#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 312#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) 313 314#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) 315#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) 316#define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE 317 318/* 319 * System Performance Counters 320 */ 321 322#define S_SPC_CFG_SRC0 0 323#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) 324#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) 325#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) 326 327#define S_SPC_CFG_SRC1 8 328#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) 329#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) 330#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) 331 332#define S_SPC_CFG_SRC2 16 333#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) 334#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) 335#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) 336 337#define S_SPC_CFG_SRC3 24 338#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) 339#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) 340#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) 341 342#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 343#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) 344 345 346/* 347 * Bus Watcher 348 */ 349 350#define S_SCD_BERR_TID 8 351#define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) 352#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) 353#define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) 354 355#define S_SCD_BERR_RID 18 356#define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) 357#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) 358#define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) 359 360#define S_SCD_BERR_DCODE 22 361#define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) 362#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) 363#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) 364 365#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) 366 367 368#define S_SCD_L2ECC_CORR_D 0 369#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) 370#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) 371#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) 372 373#define S_SCD_L2ECC_BAD_D 8 374#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) 375#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) 376#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) 377 378#define S_SCD_L2ECC_CORR_T 16 379#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) 380#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) 381#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) 382 383#define S_SCD_L2ECC_BAD_T 24 384#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) 385#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) 386#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) 387 388#define S_SCD_MEM_ECC_CORR 0 389#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) 390#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) 391#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) 392 393#define S_SCD_MEM_ECC_BAD 8 394#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) 395#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) 396#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) 397 398#define S_SCD_MEM_BUSERR 16 399#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) 400#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) 401#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) 402 403 404/* 405 * Address Trap Registers 406 */ 407 408#define M_ATRAP_INDEX _SB_MAKEMASK(4,0) 409#define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) 410 411#define S_ATRAP_CFG_CNT 0 412#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) 413#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) 414#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) 415 416#define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 417#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 418#define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) 419#define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) 420#define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 421 422#define S_ATRAP_CFG_AGENTID 8 423#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) 424#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) 425#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) 426 427#define K_BUS_AGENT_CPU0 0 428#define K_BUS_AGENT_CPU1 1 429#define K_BUS_AGENT_IOB0 2 430#define K_BUS_AGENT_IOB1 3 431#define K_BUS_AGENT_SCD 4 432#define K_BUS_AGENT_RESERVED 5 433#define K_BUS_AGENT_L2C 6 434#define K_BUS_AGENT_MC 7 435 436#define S_ATRAP_CFG_CATTR 12 437#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) 438#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) 439#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) 440 441#define K_ATRAP_CFG_CATTR_IGNORE 0 442#define K_ATRAP_CFG_CATTR_UNC 1 443#define K_ATRAP_CFG_CATTR_CACHEABLE 2 444#define K_ATRAP_CFG_CATTR_NONCOH 3 445#define K_ATRAP_CFG_CATTR_COHERENT 4 446#define K_ATRAP_CFG_CATTR_NOTUNC 5 447#define K_ATRAP_CFG_CATTR_NOTNONCOH 6 448#define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 449 450/* 451 * Trace Buffer Config register 452 */ 453 454#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) 455#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) 456#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) 457#define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) 458#define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) 459#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) 460#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) 461#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) 462#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 463#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) 464#endif /* 1250 PASS2 || 112x PASS1 */ 465 466#define S_SCD_TRACE_CFG_CUR_ADDR 10 467#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) 468#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) 469#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) 470 471/* 472 * Trace Event registers 473 */ 474 475#define S_SCD_TREVT_ADDR_MATCH 0 476#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) 477#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) 478#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) 479 480#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) 481#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) 482#define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) 483#define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) 484#define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) 485#define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) 486#define M_SCD_TREVT_READ _SB_MAKEMASK1(11) 487 488#define S_SCD_TREVT_REQID 12 489#define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) 490#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) 491#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) 492 493#define S_SCD_TREVT_RESPID 16 494#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) 495#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) 496#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) 497 498#define S_SCD_TREVT_DATAID 20 499#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) 500#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) 501#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) 502 503#define S_SCD_TREVT_COUNT 24 504#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) 505#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) 506#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) 507 508/* 509 * Trace Sequence registers 510 */ 511 512#define S_SCD_TRSEQ_EVENT4 0 513#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) 514#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) 515#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) 516 517#define S_SCD_TRSEQ_EVENT3 4 518#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) 519#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) 520#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) 521 522#define S_SCD_TRSEQ_EVENT2 8 523#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) 524#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) 525#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) 526 527#define S_SCD_TRSEQ_EVENT1 12 528#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) 529#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) 530#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) 531 532#define K_SCD_TRSEQ_E0 0 533#define K_SCD_TRSEQ_E1 1 534#define K_SCD_TRSEQ_E2 2 535#define K_SCD_TRSEQ_E3 3 536#define K_SCD_TRSEQ_E0_E1 4 537#define K_SCD_TRSEQ_E1_E2 5 538#define K_SCD_TRSEQ_E2_E3 6 539#define K_SCD_TRSEQ_E0_E1_E2 7 540#define K_SCD_TRSEQ_E0_E1_E2_E3 8 541#define K_SCD_TRSEQ_E0E1 9 542#define K_SCD_TRSEQ_E0E1E2 10 543#define K_SCD_TRSEQ_E0E1E2E3 11 544#define K_SCD_TRSEQ_E0E1_E2 12 545#define K_SCD_TRSEQ_E0E1_E2E3 13 546#define K_SCD_TRSEQ_E0E1_E2_E3 14 547#define K_SCD_TRSEQ_IGNORED 15 548 549#define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ 550 V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ 551 V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ 552 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) 553 554#define S_SCD_TRSEQ_FUNCTION 16 555#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) 556#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) 557#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) 558 559#define K_SCD_TRSEQ_FUNC_NOP 0 560#define K_SCD_TRSEQ_FUNC_START 1 561#define K_SCD_TRSEQ_FUNC_STOP 2 562#define K_SCD_TRSEQ_FUNC_FREEZE 3 563 564#define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) 565#define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) 566#define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) 567#define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) 568 569#define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) 570#define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) 571#define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) 572#define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) 573#define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) 574 575#endif 576