Searched refs:pll0 (Results 1 - 4 of 4) sorted by relevance
/openbsd-current/sys/dev/fdt/ |
H A D | imxccm.c | 655 uint32_t pll0, pll1; local 660 pll0 = regmap_read_4(sc->sc_anatop, 672 if (pll0 & CCM_INT_PLL_BYPASS) 691 uint32_t pll0, pll1, reg; local 734 pll0 = CCM_14XX_IMX8M_ARM_PLL_GNRL_CTL; 742 regmap_write_4(sc->sc_anatop, pll0, 743 regmap_read_4(sc->sc_anatop, pll0) | 745 regmap_write_4(sc->sc_anatop, pll0, 746 regmap_read_4(sc->sc_anatop, pll0) & 753 regmap_write_4(sc->sc_anatop, pll0, 1159 uint32_t pll0, pll1; local 1218 uint32_t pll0, pll1; local [all...] |
/openbsd-current/sys/dev/pci/drm/i915/display/ |
H A D | intel_dpll_mgr.h | 214 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member in struct:intel_dpll_hw_state
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H A D | intel_dpll_mgr.c | 1950 PORT_PLL_M2_INT_MASK, pll->state.hw_state.pll0); 2067 hw_state->pll0 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0)); 2068 hw_state->pll0 &= PORT_PLL_M2_INT_MASK; 2211 dpll_hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22); 2243 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, pll_state->pll0) << 22; 2333 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " 2337 hw_state->pll0,
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H A D | intel_display.c | 5329 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
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Completed in 211 milliseconds