Lines Matching refs:pll0
655 uint32_t pll0, pll1;
660 pll0 = regmap_read_4(sc->sc_anatop,
672 if (pll0 & CCM_INT_PLL_BYPASS)
691 uint32_t pll0, pll1, reg;
734 pll0 = CCM_14XX_IMX8M_ARM_PLL_GNRL_CTL;
742 regmap_write_4(sc->sc_anatop, pll0,
743 regmap_read_4(sc->sc_anatop, pll0) |
745 regmap_write_4(sc->sc_anatop, pll0,
746 regmap_read_4(sc->sc_anatop, pll0) &
753 regmap_write_4(sc->sc_anatop, pll0,
754 regmap_read_4(sc->sc_anatop, pll0) |
757 reg = regmap_read_4(sc->sc_anatop, pll0);
764 regmap_write_4(sc->sc_anatop, pll0,
765 regmap_read_4(sc->sc_anatop, pll0) &
1159 uint32_t pll0, pll1;
1167 pll0 = regmap_read_4(sc->sc_anatop, CCM_FRAC_IMX8M_ARM_PLL0);
1177 if (pll0 & CCM_FRAC_PLL_POWERDOWN)
1180 if ((pll0 & CCM_FRAC_PLL_ENABLE) == 0)
1183 mux = (pll0 >> CCM_FRAC_PLL_REFCLK_SEL_SHIFT) &
1198 if (pll0 & CCM_FRAC_PLL_BYPASS)
1201 divr_val = (pll0 >> CCM_FRAC_PLL_REFCLK_DIV_VAL_SHIFT) &
1203 divq_val = pll0 & CCM_FRAC_PLL_OUTPUT_DIV_VAL_MASK;
1218 uint32_t pll0, pll1;
1227 pll0 = CCM_FRAC_IMX8M_ARM_PLL0;
1240 reg = regmap_read_4(sc->sc_anatop, pll0);
1273 reg = regmap_read_4(sc->sc_anatop, pll0);
1277 regmap_write_4(sc->sc_anatop, pll0, reg);
1279 reg = regmap_read_4(sc->sc_anatop, pll0);
1281 regmap_write_4(sc->sc_anatop, pll0, reg);
1284 reg = regmap_read_4(sc->sc_anatop, pll0);
1296 reg = regmap_read_4(sc->sc_anatop, pll0);
1298 regmap_write_4(sc->sc_anatop, pll0, reg);