/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 25 static SDValue emitMemMem(SelectionDAG &DAG, const SDLoc &DL, unsigned Sequence, argument 41 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, 42 DAG.getConstant(Size, DL, PtrVT), 43 DAG.getConstant(Size / 256, DL, PtrVT)); 44 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, 45 DAG.getConstant(Size, DL, PtrVT)); 49 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, 56 return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP, 64 static SDValue memsetStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, argument 70 return DAG 48 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool IsVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 75 EmitTargetCodeForMemset( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Byte, SDValue Size, Align Alignment, bool IsVolatile, MachinePointerInfo DstPtrInfo) const argument 146 emitCLC(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, uint64_t Size) argument 170 addIPMSequence(const SDLoc &DL, SDValue CCReg, SelectionDAG &DAG) argument 180 EmitTargetCodeForMemcmp( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument 195 EmitTargetCodeForMemchr( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src, SDValue Char, SDValue Length, MachinePointerInfo SrcPtrInfo) const argument 221 EmitTargetCodeForStrcpy( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dest, SDValue Src, MachinePointerInfo DestPtrInfo, MachinePointerInfo SrcPtrInfo, bool isStpcpy) const argument 231 EmitTargetCodeForStrcmp( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument 249 getBoundedStrlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src, SDValue Limit) argument 262 EmitTargetCodeForStrlen( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src, MachinePointerInfo SrcPtrInfo) const argument 269 EmitTargetCodeForStrnlen( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src, SDValue MaxLength, MachinePointerInfo SrcPtrInfo) const argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.h | 1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===// 10 /// R600 DAG Lowering interface definition 35 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 39 SelectionDAG &DAG) const override; 44 const SDLoc &DL, SelectionDAG &DAG, 50 const SelectionDAG &DAG) const override; 63 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL, 68 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG, 70 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const; 72 SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) cons [all...] |
H A D | AMDGPUISelLowering.cpp | 1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===// 47 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) { argument 49 KnownBits Known = DAG.computeKnownBits(Op); 53 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) { argument 58 return VT.getSizeInBits() - DAG.ComputeNumSignBits(Op); 760 const SelectionDAG &DAG, 775 return allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(), 816 SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, 831 return TargetLowering::getNegatedExpression(Op, DAG, LegalOperation 759 isLoadBitCastBeneficial(EVT LoadTy, EVT CastTy, const SelectionDAG &DAG, const MachineMemOperand &MMO) const argument 815 getNegatedExpression( SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const argument 1152 addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const argument 1192 SelectionDAG &DAG = CLI.DAG; local 1235 Op->print(errs(), &DAG); local 1656 LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool Sign) const argument 1767 LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl<SDValue> &Results) const argument 2137 extractF64Exponent(SDValue Hi, const SDLoc &SL, SelectionDAG &DAG) argument 2294 LowerFLOG(SDValue Op, SelectionDAG &DAG, double Log2BaseInverted) const argument 2399 LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const argument 2484 LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const argument 2584 LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const argument 2774 isU24(SDValue Op, SelectionDAG &DAG) argument 2778 isI24(SDValue Op, SelectionDAG &DAG) argument 2787 SelectionDAG &DAG = DCI.DAG; local 2823 constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset, uint32_t Width, const SDLoc &DL) argument 2876 SelectionDAG &DAG = DCI.DAG; local 2933 SelectionDAG &DAG = DCI.DAG; local 2979 SelectionDAG &DAG = DCI.DAG; local 3028 SelectionDAG &DAG = DCI.DAG; local 3061 SelectionDAG &DAG = DCI.DAG; local 3159 SelectionDAG &DAG = DCI.DAG; local 3202 SelectionDAG &DAG = DCI.DAG; local 3288 getMul24(SelectionDAG &DAG, const SDLoc &SL, SDValue N0, SDValue N1, unsigned Size, bool Signed) argument 3412 getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const argument 3480 SelectionDAG &DAG = DCI.DAG; local 3498 SelectionDAG &DAG = DCI.DAG; local 3574 SelectionDAG &DAG = DCI.DAG; local 3647 SelectionDAG &DAG = DCI.DAG; local 3857 SelectionDAG &DAG = DCI.DAG; local 3894 SelectionDAG &DAG = DCI.DAG; local 4100 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT, const SDLoc &SL, bool RawReg) const argument 4136 loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const argument 4152 storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) const argument 4166 loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const argument 4358 getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const argument 4376 getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const argument 4397 computeKnownBitsForTargetNode( const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument 4540 ComputeNumSignBitsForTargetNode( SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument 4605 isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN, unsigned Depth) const argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblySelectionDAGInfo.cpp | 22 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, 25 auto &ST = DAG.getMachineFunction().getSubtarget<WebAssemblySubtarget>(); 29 SDValue MemIdx = DAG.getConstant(0, DL, MVT::i32); 31 return DAG.getNode(WebAssemblyISD::MEMORY_COPY, DL, MVT::Other, 33 DAG.getZExtOrTrunc(Size, DL, LenMVT)}); 37 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, 40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, 46 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Val, 49 auto &ST = DAG.getMachineFunction().getSubtarget<WebAssemblySubtarget>(); 53 SDValue MemIdx = DAG 21 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool IsVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 36 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool IsVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 45 EmitTargetCodeForMemset( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Val, SDValue Size, Align Alignment, bool IsVolatile, MachinePointerInfo DstPtrInfo) const argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
H A D | XCoreSelectionDAGInfo.cpp | 19 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, 25 DAG.MaskedValueIsZero(Size, APInt(SizeBitWidth, 3))) { 26 const TargetLowering &TLI = *DAG.getSubtarget().getTargetLowering(); 29 Entry.Ty = DAG.getDataLayout().getIntPtrType(*DAG.getContext()); 34 TargetLowering::CallLoweringInfo CLI(DAG); 38 Type::getVoidTy(*DAG.getContext()), 39 DAG.getExternalSymbol( 40 "__memcpy_4", TLI.getPointerTy(DAG.getDataLayout())), 18 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
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H A D | XCoreISelLowering.cpp | 1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===// 198 LowerOperation(SDValue Op, SelectionDAG &DAG) const { 201 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 202 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 203 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 204 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 205 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 206 case ISD::LOAD: return LowerLOAD(Op, DAG); 207 case ISD::STORE: return LowerSTORE(Op, DAG); 208 case ISD::VAARG: return LowerVAARG(Op, DAG); 404 isWordAligned(SDValue Value, SelectionDAG &DAG) argument 1032 SelectionDAG &DAG = CLI.DAG; local 1060 LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl<CCValAssign> &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument 1106 LowerCCCCallTo( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1240 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1259 LowerCCCArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1591 SelectionDAG &DAG = DCI.DAG; local 1814 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument [all...] |
H A D | XCoreISelLowering.h | 1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===// 10 // selection DAG. 107 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 113 SelectionDAG &DAG) const override; 116 // DAG node. 149 const SDLoc &dl, SelectionDAG &DAG, 157 const SDLoc &dl, SelectionDAG &DAG, 159 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 161 SelectionDAG &DAG) const; 165 SelectionDAG &DAG) cons [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.h | 1 //===-- LanaiISelLowering.h - Lanai DAG Lowering Interface -....-*- C++ -*-===// 10 // selection DAG. 72 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 75 // DAG node. 78 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 79 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 80 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 81 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 82 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 83 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) cons [all...] |
H A D | LanaiISelLowering.cpp | 1 //===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===// 176 SelectionDAG &DAG) const { 179 return LowerMUL(Op, DAG); 181 return LowerBR_CC(Op, DAG); 183 return LowerConstantPool(Op, DAG); 185 return LowerGlobalAddress(Op, DAG); 187 return LowerBlockAddress(Op, DAG); 189 return LowerJumpTable(Op, DAG); 191 return LowerSELECT_CC(Op, DAG); 193 return LowerSETCC(Op, DAG); 396 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 411 SelectionDAG &DAG = CLI.DAG; local 437 LowerCCCArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 596 LowerCCCCallTo( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg, bool , const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 774 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 801 IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG) argument 1347 isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG) argument 1421 SelectionDAG &DAG = DCI.DAG; local 1488 computeKnownBitsForTargetNode( const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 32 SelectionDAG &DAG, ArrayRef<MCPhysReg> ClobberSet) const { 38 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 43 DAG.getSubtarget().getRegisterInfo()); 48 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Val, 53 DAG.getMachineFunction().getSubtarget<X86Subtarget>(); 59 assert(!isBaseRegConflictPossible(DAG, ClobberSet)); 75 ? DAG.getTargetLoweringInfo().getLibcallName(RTLIB::BZERO) 77 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 78 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout()); 79 Type *IntPtrTy = DAG 31 isBaseRegConflictPossible( SelectionDAG &DAG, ArrayRef<MCPhysReg> ClobberSet) const argument 47 EmitTargetCodeForMemset( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Val, SDValue Size, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument 185 emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, MVT AVT) argument 207 emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size) argument 235 emitConstantSizeRepmov( SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, EVT SizeVT, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) argument 291 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument [all...] |
H A D | X86ISelLowering.cpp | 1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 10 // selection DAG. 106 static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl, argument 108 MachineFunction &MF = DAG.getMachineFunction(); 109 DAG.getContext()->diagnose( 1182 // so that DAG combine doesn't try to turn it into uint_to_fp. 2095 SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, argument 2097 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 2099 MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val); 2436 SelectionDAG &DAG) cons 2621 lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc, const SDLoc &Dl, SelectionDAG &DAG) argument 2652 Passv64i1ArgInRegs( const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg, SmallVectorImpl<std::pair<Register, SDValue>> &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, const X86Subtarget &Subtarget) argument 2945 getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, const SDLoc &Dl, const X86Subtarget &Subtarget, SDValue *InFlag = nullptr) argument 2996 lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT, const EVT &ValLoc, const SDLoc &Dl, SelectionDAG &DAG) argument 3032 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, uint32_t *RegMask) const argument 3173 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) argument 3231 LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo &MFI, unsigned i) const argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
H A D | BPFSelectionDAGInfo.cpp | 21 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, 35 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 37 Dst = DAG.getNode(BPFISD::MEMCPY, dl, VTs, Chain, Dst, Src, 38 DAG.getConstant(CopyLen, dl, MVT::i64), 39 DAG.getConstant(Alignment.value(), dl, MVT::i64)); 20 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==// 10 // selection DAG. 498 const SelectionDAG &DAG, 503 // *DAG* representation of pointers will always be 64-bits. They will be 504 // truncated and extended when transferred to memory, but the 64-bit DAG 528 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 552 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 703 const SelectionDAG &DAG) const override { 707 bool NoFloat = DAG.getMachineFunction().getFunction().hasFnAttribute( 742 SelectionDAG &DAG) cons [all...] |
H A D | AArch64SelectionDAGInfo.cpp | 19 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, 26 DAG.getMachineFunction().getSubtarget<AArch64Subtarget>(); 28 ? DAG.getTargetLoweringInfo().getLibcallName(RTLIB::BZERO) : nullptr; 34 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout()); 35 Type *IntPtrTy = Type::getInt8PtrTy(*DAG.getContext()); 43 TargetLowering::CallLoweringInfo CLI(DAG); 46 .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), 47 DAG.getExternalSymbol(bzeroName, IntPtr), 58 static SDValue EmitUnrolledSetTag(SelectionDAG &DAG, const SDLoc &dl, argument 62 MachineFunction &MF = DAG 18 EmitTargetCodeForMemset( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument 110 EmitTargetCodeForSetTag( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Addr, SDValue Size, MachinePointerInfo DstPtrInfo, bool ZeroData) const argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
H A D | M68kISelLowering.h | 1 //===-- M68kISelLowering.h - M68k DAG Lowering Interface ----*- C++ -*-===// 11 /// selection DAG. 30 /// M68k Specific DAG nodes 137 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 151 SelectionDAG &DAG) const override; 168 SelectionDAG &DAG) const override; 176 SelectionDAG &DAG) const; 178 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 182 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 188 SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunctio [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | MacroFusion.cpp | 9 /// \file This file contains the implementation of the DAG scheduling mutation 54 static bool fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU, argument 71 if (!DAG.addEdge(&SecondSU, SDep(&FirstSU, SDep::Cluster))) 92 dbgs() << "Macro fuse: "; DAG.dumpNodeName(FirstSU); dbgs() << " - "; 93 DAG.dumpNodeName(SecondSU); dbgs() << " / "; 94 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " 95 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); 99 if (&SecondSU != &DAG.ExitSU) 103 SU == &DAG.ExitSU || SU == &SecondSU || SU->isPred(&SecondSU)) 105 LLVM_DEBUG(dbgs() << " Bind "; DAG 154 apply(ScheduleDAGInstrs *DAG) argument 168 scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU) argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
H A D | VEISelLowering.h | 1 //===-- VEISelLowering.h - VE DAG Lowering Interface ------------*- C++ -*-===// 10 // selection DAG. 75 const SDLoc &dl, SelectionDAG &DAG, 88 SelectionDAG &DAG) const override; 103 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 110 SelectionDAG &DAG) const override; 114 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 115 SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const; 116 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 117 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) cons [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.h | 1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===// 10 // selection DAG. 126 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const; 158 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 160 SelectionDAG &DAG) const override; 162 SelectionDAG &DAG) const override; 166 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 167 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 168 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 169 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) cons [all...] |
H A D | HexagonISelLoweringHVX.cpp | 41 // nodes, which would be unoptimizable by the DAG combiner. 315 const SDLoc &dl, SelectionDAG &DAG) const { 317 IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32)); 319 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps); 356 SelectionDAG &DAG) const { 360 return DAG.getBitcast(CastTy, Vec); 365 SelectionDAG &DAG) const { 366 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), 372 SelectionDAG &DAG) const { 376 return DAG [all...] |
H A D | HexagonSelectionDAGInfo.cpp | 20 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, 33 const TargetLowering &TLI = *DAG.getSubtarget().getTargetLowering(); 36 Entry.Ty = DAG.getDataLayout().getIntPtrType(*DAG.getContext()); 46 const MachineFunction &MF = DAG.getMachineFunction(); 50 TargetLowering::CallLoweringInfo CLI(DAG); 55 Type::getVoidTy(*DAG.getContext()), 56 DAG.getTargetExternalSymbol( 57 SpecialMemcpyName, TLI.getPointerTy(DAG.getDataLayout()), Flags), 19 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 10 // selection DAG. 199 const SDLoc &DL, SelectionDAG &DAG) const { 201 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 202 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 210 const SDLoc &DL, SelectionDAG &DAG) const { 211 MachineFunction &MF = DAG.getMachineFunction(); 217 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 218 *DAG.getContext()); 242 SDValue Part0 = DAG 367 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 381 LowerFormalArguments_32( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 576 LowerFormalArguments_64( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 692 hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, const CallBase *Call) argument 717 SelectionDAG &DAG = CLI.DAG; local 1864 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument 2153 LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const argument 2303 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument 2319 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument 2336 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument 2365 LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument 2393 LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument 2414 LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument 2433 LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument 2470 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument 2506 LowerVASTART(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument 2526 LowerVAARG(SDValue Op, SelectionDAG &DAG) argument 2550 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument 2615 getFLUSHW(SDValue Op, SelectionDAG &DAG) argument 2622 getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget, bool AlwaysFlush = false) argument 2655 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument 2664 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget) argument 2699 LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG, unsigned opcode) argument 2733 LowerF128Load(SDValue Op, SelectionDAG &DAG) argument 2774 LowerLOAD(SDValue Op, SelectionDAG &DAG) argument 2786 LowerF128Store(SDValue Op, SelectionDAG &DAG) argument 2822 LowerSTORE(SDValue Op, SelectionDAG &DAG) argument 2845 LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) argument 2888 LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) argument 2939 LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument 2987 LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.h | 1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 10 // selection DAG. 590 SelectionDAG &DAG); 595 SelectionDAG &DAG); 600 SelectionDAG &DAG); 605 unsigned ShuffleKind, SelectionDAG &DAG); 610 unsigned ShuffleKind, SelectionDAG &DAG); 615 unsigned ShuffleKind, SelectionDAG &DAG); 645 SelectionDAG &DAG); 666 SelectionDAG &DAG); [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 1 //===- ARCISelLowering.cpp - ARC DAG Lowering Impl --------------*- C++ -*-===// 37 SDLoc dl, SelectionDAG &DAG, 162 SDValue ARCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 171 SDValue Cmp = DAG.getNode(ARCISD::CMP, dl, MVT::Glue, LHS, RHS); 172 return DAG.getNode(ARCISD::CMOV, dl, TVal.getValueType(), TVal, FVal, 173 DAG.getConstant(ArcCC, dl, MVT::i32), Cmp); 177 SelectionDAG &DAG) const { 189 SDValue LS = DAG.getNode(ISD::SHL, dl, MVT::i32, Op0, 190 DAG.getConstant(32 - Width, dl, MVT::i32)); 191 SDValue SR = DAG 224 SelectionDAG &DAG = CLI.DAG; local 369 lowerCallResult(SDValue Chain, SDValue Glue, const SmallVectorImpl<CCValAssign> &RVLocs, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument 430 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 445 LowerCallArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 734 LowerVASTART(SDValue Op, SelectionDAG &DAG) argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | ScheduleDAGMutation.h | 21 /// Mutate the DAG as a postpass after normal DAG building. 28 virtual void apply(ScheduleDAGInstrs *DAG) = 0;
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H A D | SelectionDAGAddressAnalysis.h | 1 //===- SelectionDAGAddressAnalysis.h - DAG Address Analysis -----*- C++ -*-===// 57 bool equalBaseIndex(const BaseIndexOffset &Other, const SelectionDAG &DAG, 61 const SelectionDAG &DAG) const { 63 return equalBaseIndex(Other, DAG, Off); 68 bool contains(const SelectionDAG &DAG, int64_t BitSize, 72 bool contains(const SelectionDAG &DAG, int64_t BitSize, argument 75 return contains(DAG, BitSize, Other, OtherBitSize, BitOffset); 84 const SelectionDAG &DAG, bool &IsAlias); 87 static BaseIndexOffset match(const SDNode *N, const SelectionDAG &DAG);
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