Searched refs:sclk (Results 1 - 25 of 157) sorted by last modified time

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/linux-master/drivers/clk/meson/
H A Dsclk-div.c23 #include "sclk-div.h"
31 static int sclk_div_maxval(struct meson_sclk_div_data *sclk) argument
33 return (1 << sclk->div.width) - 1;
36 static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk) argument
38 return sclk_div_maxval(sclk) + 1;
51 struct meson_sclk_div_data *sclk)
61 maxdiv = sclk_div_maxdiv(sclk);
92 bestdiv = sclk_div_maxdiv(sclk);
103 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
106 div = sclk_div_bestdiv(hw, req->rate, &req->best_parent_rate, sclk);
49 sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate, unsigned long *prate, struct meson_sclk_div_data *sclk) argument
112 sclk_apply_ratio(struct clk_regmap *clk, struct meson_sclk_div_data *sclk) argument
129 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
143 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
158 sclk_apply_divider(struct clk_regmap *clk, struct meson_sclk_div_data *sclk) argument
171 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
186 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
194 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
204 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
212 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
223 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
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H A DMakefile13 obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
/linux-master/drivers/clk/
H A Dclk-scmi.c212 static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk, argument
220 .num_parents = sclk->info->num_parents,
222 .name = sclk->info->name,
223 .parent_data = sclk->parent_data,
226 sclk->hw.init = &init;
227 ret = devm_clk_hw_register(dev, &sclk->hw);
231 if (sclk->info->rate_discrete) {
232 int num_rates = sclk->info->list.num_rates;
237 min_rate = sclk->info->list.rates[0];
238 max_rate = sclk
336 scmi_clk_ops_select(struct scmi_clk *sclk, bool atomic_capable, unsigned int atomic_threshold_us, const struct clk_ops **clk_ops_db, size_t db_size) argument
422 struct scmi_clk *sclk; local
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/linux-master/sound/soc/xilinx/
H A Dxlnx_i2s.c98 unsigned int bits_per_sample, sclk, sclk_div; local
105 sclk = params_rate(params) * bits_per_sample * params_channels(params);
106 sclk_div = drv_data->sysclk / sclk / 2;
108 if ((drv_data->sysclk % sclk != 0) ||
110 dev_warn(i2s_dai->dev, "invalid SCLK divisor for sysclk %u and sclk %u\n",
111 drv_data->sysclk, sclk);
/linux-master/sound/soc/intel/boards/
H A Dkbl_rt5663_rt5514_max98927.c57 struct clk *sclk; member in struct:kbl_codec_private
109 ret = clk_set_rate(priv->sclk, 3072000);
111 dev_err(card->dev, "Can't set rate for sclk, err: %d\n",
117 ret = clk_prepare_enable(priv->sclk);
119 dev_err(card->dev, "Can't enable sclk, err: %d\n", ret);
125 clk_disable_unprepare(priv->sclk);
832 ctx->sclk = devm_clk_get(&pdev->dev, "ssp1_sclk");
833 if (IS_ERR(ctx->sclk)) {
834 ret = PTR_ERR(ctx->sclk);
H A Dkbl_rt5663_max98927.c47 struct clk *sclk; member in struct:kbl_rt5663_private
99 ret = clk_set_rate(priv->sclk, 3072000);
101 dev_err(card->dev, "Can't set rate for sclk, err: %d\n",
107 ret = clk_prepare_enable(priv->sclk);
109 dev_err(card->dev, "Can't enable sclk, err: %d\n", ret);
115 clk_disable_unprepare(priv->sclk);
1027 ctx->sclk = devm_clk_get(&pdev->dev, "ssp1_sclk");
1028 if (IS_ERR(ctx->sclk)) {
1029 ret = PTR_ERR(ctx->sclk);
/linux-master/sound/soc/codecs/
H A Dtas5086.c241 unsigned int mclk, sclk; member in struct:tas5086_private
307 priv->sclk = freq;
394 (priv->sclk == 48 * priv->rate) ?
H A Drt5682s.c1113 static int get_clk_info(int sclk, int rate) argument
1118 if (sclk <= 0 || rate <= 0)
1123 if (sclk == rate * pd[i])
H A Drt1308.c435 static int rt1308_get_clk_info(int sclk, int rate) argument
440 if (sclk <= 0 || rate <= 0)
445 if (sclk == rate * pd[i])
H A Drt1305.c607 static int rt1305_get_clk_info(int sclk, int rate) argument
612 if (sclk <= 0 || rate <= 0)
617 if (sclk == rate * pd[i])
H A Drt1011.c1556 static int rt1011_get_clk_info(int sclk, int rate) argument
1561 if (sclk <= 0 || rate <= 0)
1566 if (sclk == rate * pd[i])
H A Dnau8822.c674 int i, sclk, imclk; local
685 sclk = (nau8822->sysclk * 10) / nau8822_mclk_scaler[i];
686 if (sclk < imclk)
H A Dnau8810.c668 int i, sclk, imclk = rate * 256, div = 0; local
680 sclk = (nau8810->sysclk * 10) /
682 if (sclk < imclk)
H A Dcs43130.c878 unsigned int sclk = cs43130->dais[dai->id].sclk; local
909 sclk = params_rate(params) * bitwidth_dai *
954 if (!sclk && cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM)
956 sclk = params_rate(params) * bitwidth_dai *
959 if (!sclk) {
965 bitwidth_sclk = (sclk / params_rate(params)) / params_channels(params);
972 "sclk = %u, fs = %d, bitwidth_dai = %u\n",
973 sclk, params_rate(params), bitwidth_dai);
1611 cs43130->dais[codec_dai->id].sclk
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H A Dcs35l35.c549 if ((cs35l35->sclk / srate) % 4) {
550 dev_err(component->dev, "Unsupported sclk/fs ratio %d:%d\n",
551 cs35l35->sclk, srate);
554 sp_sclks = ((cs35l35->sclk / srate) / 4) - 1;
655 cs35l35->sclk = freq;
/linux-master/sound/aoa/soundbus/i2sbus/
H A Dpcm.c34 static int clock_and_divisors(int mclk, int sclk, int rate, int *out) argument
36 /* sclk must be derived from mclk! */
37 if (mclk % sclk)
39 /* derive sclk register value */
40 if (i2s_sf_sclkdiv(mclk / sclk, out))
/linux-master/drivers/mmc/host/
H A Dmtk-sd.c809 /* in 1048576 sclk cycle unit */
882 u32 sclk; local
911 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
914 sclk = (host->src_clk_freq >> 2) / div;
926 sclk = host->src_clk_freq >> 1;
932 sclk = host->src_clk_freq;
937 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
940 sclk
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/linux-master/drivers/gpu/drm/radeon/
H A Drv515.c920 fixed20_12 sclk; member in struct:rv515_watermark
932 fixed20_12 sclk; local
948 /* sclk in Mhz */
950 sclk.full = dfixed_const(selected_sclk);
951 sclk.full = dfixed_div(sclk, a);
1015 * sclk = system clock(Mhz)
1018 chunk_time.full = dfixed_div(a, sclk);
1103 fill_rate.full = dfixed_div(wm0->sclk, a);
1151 fill_rate.full = dfixed_div(wm0->sclk,
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H A Dradeon_pm.c175 u32 sclk, mclk; local
183 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
184 clock_info[rdev->pm.requested_clock_mode_index].sclk;
185 if (sclk > rdev->pm.default_sclk)
186 sclk = rdev->pm.default_sclk;
207 if (sclk < rdev->pm.current_sclk)
224 if (sclk != rdev->pm.current_sclk) {
226 radeon_set_engine_clock(rdev, sclk);
228 rdev->pm.current_sclk = sclk;
229 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
719 u32 sclk = 0; local
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H A Dradeon.h1157 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1259 u32 delay; /* delay in usec from voltage drop to sclk change */
1278 u32 sclk; member in struct:radeon_pm_clock_info
1363 u32 sclk; member in struct:radeon_blacklist_clocks
1369 u32 sclk; member in struct:radeon_clock_and_voltage_limits
1409 u32 sclk; member in struct:radeon_phase_shedding_limits_entry
1523 u32 sclk; member in struct:radeon_vce_state
1601 fixed20_12 sclk; member in struct:radeon_pm
H A Dr600.c528 clock_info[rdev->pm.requested_clock_mode_index].sclk,
1845 /* set mclk/sclk to bypass */
H A Dr100.c299 clock_info[rdev->pm.requested_clock_mode_index].sclk,
3259 sclk_ff = rdev->pm.sclk;
/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dhwmgr.h522 uint32_t sclk; member in struct:phm_clock_and_voltage_limits
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_hwmgr.c498 "Failed to init sclk threshold!",
2797 info->engine_max_clock = max_limits->sclk;
2993 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
H A Dvega12_hwmgr.c463 "Failed to init sclk threshold!",
1824 info->engine_max_clock = max_limits->sclk;

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