/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { argument 74 switch ((Imm >> 6) & 0x7) { 85 static inline unsigned getShiftValue(unsigned Imm) { argument 86 return Imm & 0x3f; 99 unsigned Imm) { 100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); 110 return (STEnc << 6) | (Imm & 0x3f); 118 static inline unsigned getArithShiftValue(unsigned Imm) { argument 119 return Imm 98 getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm) argument 123 getExtendType(unsigned Imm) argument 138 getArithExtendType(unsigned Imm) argument 170 getArithExtendImm(AArch64_AM::ShiftExtendType ET, unsigned Imm) argument 178 getMemDoShift(unsigned Imm) argument 184 getMemExtendType(unsigned Imm) argument 213 processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t &Encoding) argument 343 getFPImmFloat(unsigned Imm) argument 367 getFP16Imm(const APInt &Imm) argument 393 getFP32Imm(const APInt &Imm) argument 421 getFP64Imm(const APInt &Imm) argument 451 isAdvSIMDModImmType1(uint64_t Imm) argument 456 encodeAdvSIMDModImmType1(uint64_t Imm) argument 460 decodeAdvSIMDModImmType1(uint8_t Imm) argument 466 isAdvSIMDModImmType2(uint64_t Imm) argument 471 encodeAdvSIMDModImmType2(uint64_t Imm) argument 475 decodeAdvSIMDModImmType2(uint8_t Imm) argument 481 isAdvSIMDModImmType3(uint64_t Imm) argument 486 encodeAdvSIMDModImmType3(uint64_t Imm) argument 490 decodeAdvSIMDModImmType3(uint8_t Imm) argument 496 isAdvSIMDModImmType4(uint64_t Imm) argument 501 encodeAdvSIMDModImmType4(uint64_t Imm) argument 505 decodeAdvSIMDModImmType4(uint8_t Imm) argument 511 isAdvSIMDModImmType5(uint64_t Imm) argument 517 encodeAdvSIMDModImmType5(uint64_t Imm) argument 521 decodeAdvSIMDModImmType5(uint8_t Imm) argument 527 isAdvSIMDModImmType6(uint64_t Imm) argument 533 encodeAdvSIMDModImmType6(uint64_t Imm) argument 537 decodeAdvSIMDModImmType6(uint8_t Imm) argument 543 isAdvSIMDModImmType7(uint64_t Imm) argument 548 encodeAdvSIMDModImmType7(uint64_t Imm) argument 552 decodeAdvSIMDModImmType7(uint8_t Imm) argument 558 isAdvSIMDModImmType8(uint64_t Imm) argument 563 decodeAdvSIMDModImmType8(uint8_t Imm) argument 568 encodeAdvSIMDModImmType8(uint64_t Imm) argument 573 isAdvSIMDModImmType9(uint64_t Imm) argument 579 encodeAdvSIMDModImmType9(uint64_t Imm) argument 583 decodeAdvSIMDModImmType9(uint8_t Imm) argument 593 isAdvSIMDModImmType10(uint64_t Imm) argument 613 encodeAdvSIMDModImmType10(uint64_t Imm) argument 641 decodeAdvSIMDModImmType10(uint8_t Imm) argument 655 isAdvSIMDModImmType11(uint64_t Imm) argument 662 encodeAdvSIMDModImmType11(uint64_t Imm) argument 690 decodeAdvSIMDModImmType11(uint8_t Imm) argument 705 isAdvSIMDModImmType12(uint64_t Imm) argument 711 encodeAdvSIMDModImmType12(uint64_t Imm) argument 739 decodeAdvSIMDModImmType12(uint8_t Imm) argument 755 isSVEMaskOfIdenticalElements(int64_t Imm) argument 762 isSVECpyImm(int64_t Imm) argument 777 isSVEAddSubImm(int64_t Imm) argument 783 isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Utils/ |
H A D | RISCVMatInt.h | 22 int64_t Imm; member in struct:llvm::RISCVMatInt::Inst 24 Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {} argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVTargetTransformInfo.cpp | 18 int RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, argument 24 if (Imm == 0) 29 return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty), 33 int RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, argument 39 if (Imm == 0) 75 if (Imm.getMinSignedBits() <= 64 && 76 getTLI()->isLegalAddImmediate(Imm.getSExtValue())) { 82 return getIntImmCost(Imm, Ty, CostKind); 90 const APInt &Imm, Type *Ty, 89 getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) argument
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H A D | RISCVTargetTransformInfo.h | 44 int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind); 45 int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, 47 int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsAnalyzeImmediate.cpp | 32 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, argument 34 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); 35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); 38 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, argument 40 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); 41 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); 44 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, argument 46 unsigned Shamt = countTrailingZeros(Imm); 47 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); 51 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigne argument 129 Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu) argument [all...] |
H A D | MipsAnalyzeImmediate.h | 26 /// Analyze - Get an instruction sequence to load immediate Imm. The last 29 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu); 38 /// load immediate Imm 39 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 42 /// load immediate Imm 43 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 46 /// load immediate Imm 47 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 49 /// GetInstSeqLs - Get instruction sequences to load immediate Imm. 50 void GetInstSeqLs(uint64_t Imm, unsigne [all...] |
H A D | MipsISelDAGToDAG.h | 98 virtual bool selectVSplat(SDNode *N, APInt &Imm, 101 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const; 103 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const; 105 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const; 107 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const; 109 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const; 111 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const; 113 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const; 115 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const; 117 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) cons 138 getImm(const SDNode *Node, uint64_t Imm) argument [all...] |
H A D | MipsSEISelDAGToDAG.h | 96 bool selectVSplat(SDNode *N, APInt &Imm, 99 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed, 102 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override; 104 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override; 106 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override; 108 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override; 110 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override; 112 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override; 114 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override; 116 bool selectVSplatSimm5(SDValue N, SDValue &Imm) cons [all...] |
H A D | MipsISelDAGToDAG.cpp | 154 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, argument 160 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const { 165 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const { 170 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const { 175 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const { 180 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const { 185 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const { 190 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const { 195 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const { 200 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) cons [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAddressingModes.h | 112 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { 113 return ShOp | (Imm << 3); 120 inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; } 123 inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; } 125 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, 129 inline unsigned getSOImmValRotate(unsigned Imm) { argument 132 if ((Imm & ~255U) == 0) return 0; 135 unsigned TZ = countTrailingZeros(Imm); 210 getThumbImmValShift(unsigned Imm) argument 229 getThumbImm16ValShift(unsigned Imm) argument 263 unsigned u, Vs, Imm; local 327 isT2SOImmTwoPartVal(unsigned Imm) argument 354 getT2SOImmTwoPartFirst(unsigned Imm) argument 371 getT2SOImmTwoPartSecond(unsigned Imm) argument 630 getFPImmFloat(unsigned Imm) argument 653 getFP16Imm(const APInt &Imm) argument 679 getFP32Imm(const APInt &Imm) argument 707 getFP64Imm(const APInt &Imm) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86ShuffleDecode.h | 31 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 52 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm, 55 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm, 58 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm, 61 void DecodeVALIGNMask(unsigned NumElts, unsigned Imm, 65 void DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, 69 void DecodePSHUFHWMask(unsigned NumElts, unsigned Imm, 73 void DecodePSHUFLWMask(unsigned NumElts, unsigned Imm, 80 void DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, 104 void DecodeBLENDMask(unsigned NumElts, unsigned Imm, [all...] |
H A D | X86ShuffleDecode.cpp | 25 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument 33 unsigned ZMask = Imm & 15; 34 unsigned CountD = (Imm >> 4) & 3; 35 unsigned CountS = (Imm >> 6) & 3; 98 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm, argument 105 if (i >= Imm) M = i - Imm + l; 110 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm, argument 116 unsigned Base = i + Imm; 123 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm, argument 137 DecodeVALIGNMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 146 DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 162 DecodePSHUFHWMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 176 DecodePSHUFLWMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 199 DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 262 decodeVSHUF64x2FamilyMask(unsigned NumElts, unsigned ScalarSize, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 279 DecodeVPERM2X128Mask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 313 DecodeBLENDMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 362 DecodeVPERMMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandImm.h | 28 void expandMOVImm(uint64_t Imm, unsigned BitSize,
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H A D | AArch64ExpandImm.cpp | 23 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) { argument 26 return (Imm >> (ChunkIdx * 16)) & 0xFFFF; 126 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) { argument 131 Imm &= ~(Mask << (Idx * 16)); 134 Imm |= Mask << (Idx * 16); 136 return Imm; 246 static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize, argument 260 Imm = ~Imm; 265 Imm 305 expandMOVImm(uint64_t Imm, unsigned BitSize, SmallVectorImpl<ImmInsnModel> &Insn) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiTargetTransformInfo.h | 52 int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) { argument 54 if (Imm == 0) 56 if (isInt<16>(Imm.getSExtValue())) 58 if (isInt<21>(Imm.getZExtValue())) 60 if (isInt<32>(Imm.getSExtValue())) { 61 if ((Imm.getSExtValue() & 0xFFFF) == 0) 69 int getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, argument 71 return getIntImmCost(Imm, Ty, CostKind); 74 int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, argument 76 return getIntImmCost(Imm, T [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/ |
H A D | PPCDisassembler.cpp | 63 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, argument 66 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm))); 70 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, argument 73 int32_t Offset = SignExtend32<24>(Imm); 186 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 188 assert(isUInt<N>(Imm) && "Invalid immediate"); 189 Inst.addOperand(MCOperand::createImm(Imm)); 194 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 196 assert(isUInt<N>(Imm) && "Invalid immediate"); 197 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/ |
H A D | NVPTXInstPrinter.cpp | 101 int64_t Imm = MO.getImm(); local 105 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) 109 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) 113 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { 151 int64_t Imm = MO.getImm(); local 155 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG) 158 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) { 225 int Imm = (int) MO.getImm(); local 227 if (Imm) 230 switch (Imm) { 276 int Imm = (int)MO.getImm(); local 278 O << Imm; // Just print out PTX version local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUInstPrinter.cpp | 76 int64_t Imm = MI->getOperand(OpNo).getImm(); local 77 if (isInt<16>(Imm) || isUInt<16>(Imm)) 78 O << formatHex(static_cast<uint64_t>(Imm & 0xffff)); 137 uint16_t Imm = MI->getOperand(OpNo).getImm(); local 138 if (Imm != 0) { 147 uint16_t Imm = MI->getOperand(OpNo).getImm(); local 148 if (Imm != 0) { 381 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm, argument 384 int16_t SImm = static_cast<int16_t>(Imm); 391 printImmediate16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) argument 423 printImmediateV216(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) argument 430 printImmediate32(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) argument 464 printImmediate64(uint64_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) argument 506 unsigned Imm = MI->getOperand(OpNo).getImm(); local 516 unsigned Imm = MI->getOperand(OpNo).getImm(); local 526 unsigned Imm = MI->getOperand(OpNo).getImm(); local 741 unsigned Imm = MI->getOperand(OpNo).getImm(); local 754 unsigned Imm = MI->getOperand(OpNo).getImm(); local 851 unsigned Imm = MI->getOperand(OpNo).getImm(); local 861 unsigned Imm = MI->getOperand(OpNo).getImm(); local 871 unsigned Imm = MI->getOperand(OpNo).getImm(); local 911 unsigned Imm = MI->getOperand(OpNo).getImm(); local 1090 unsigned Imm = MI->getOperand(OpNum).getImm(); local 1102 O << "invalid_param_" << Imm; local 1188 int Imm = MI->getOperand(OpNo).getImm(); local 1389 uint16_t Imm = MI->getOperand(OpNo).getImm(); local 1478 int64_t Imm = Op.getImm(); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/ |
H A D | SystemZDisassembler.cpp | 171 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { 172 if (!isUInt<N>(Imm)) 174 Inst.addOperand(MCOperand::createImm(Imm)); 179 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { 180 if (!isUInt<N>(Imm)) 182 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 186 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, 188 return decodeUImmOperand<1>(Inst, Imm); 191 static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm, 193 return decodeUImmOperand<2>(Inst, Imm); [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/ |
H A D | BPFInstPrinter.cpp | 76 auto Imm = OffsetOp.getImm(); local 77 if (Imm >= 0) 78 O << " + " << formatImm(Imm); 80 O << " - " << formatImm(-Imm); 101 int16_t Imm = Op.getImm(); local 102 O << ((Imm >= 0) ? "+" : "") << formatImm(Imm);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
H A D | RISCVDisassembler.cpp | 200 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, argument 202 assert(isUInt<N>(Imm) && "Invalid immediate"); 204 Inst.addOperand(MCOperand::createImm(Imm)); 209 static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm, argument 212 if (Imm == 0) 214 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder); 218 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, argument 220 assert(isUInt<N>(Imm) && "Invalid immediate"); 222 // Sign-extend the number in the bottom N bits of Imm 223 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 228 decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument 237 decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument 248 decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument 259 decodeFRMArg(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
H A D | RISCVAsmParser.cpp | 303 ImmOp Imm; member in union:__anon4287::RISCVOperand::__anon4288 321 Imm = o.Imm; 350 static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm, argument 354 return RE->evaluateAsConstant(Imm); 359 Imm = CE->getValue(); 369 int64_t Imm; local 373 bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); 376 IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm); 378 IsValid = isShiftedInt<N - 1, 1>(Imm); 385 int64_t Imm; local 395 int64_t Imm; local 406 int64_t Imm; local 416 int64_t Imm; local 469 int64_t Imm; local 483 int64_t Imm; local 494 int64_t Imm; local 507 int64_t Imm; local 518 int64_t Imm; local 527 int64_t Imm; local 540 int64_t Imm; local 549 int64_t Imm; local 559 int64_t Imm; local 630 int64_t Imm; local 661 int64_t Imm; local 679 int64_t Imm; local 714 int64_t Imm; local 871 int64_t Imm = 0; local 894 int64_t Imm = 0; local 907 unsigned Imm = 0; local 1312 int64_t Imm = CE->getValue(); local 2373 int64_t Imm = Inst.getOperand(1).getImm(); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | MIRFormatter.h | 38 Optional<unsigned> OpIdx, int64_t Imm) const { 39 OS << Imm; local 45 StringRef Src, int64_t &Imm, 44 parseImmMnemonic(const unsigned OpCode, const unsigned OpIdx, StringRef Src, int64_t &Imm, ErrorCallbackType ErrorCallback) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyRegNumbering.cpp | 78 int64_t Imm = MI.getOperand(1).getImm(); local 80 << " -> WAReg " << Imm << "\n"); 81 MFI.setWAReg(MI.getOperand(0).getReg(), Imm);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
H A D | LanaiMCTargetDesc.cpp | 103 int64_t Imm = Inst.getOperand(0).getImm(); variable 104 Target = Addr + Size + Imm; 107 int64_t Imm = Inst.getOperand(0).getImm(); variable 111 if (Imm == 0) 114 Target = Imm;
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