Searched refs:WRITE_REG32 (Results 1 - 12 of 12) sorted by relevance
/freebsd-12-stable/sys/dev/qlxge/ |
H A D | qls_hw.c | 271 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); 272 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower); 281 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); 282 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_upper); 291 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); 297 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, value); 336 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); 337 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower); 347 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); 348 WRITE_REG32(h [all...] |
H A D | qls_dump.c | 408 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg | Q81_CTL_PROC_ADDR_READ); 432 WRITE_REG32(ha, Q81_CTL_PROC_DATA, data); 434 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg); 616 WRITE_REG32(ha, Q81_CTL_XG_SERDES_ADDR, \ 822 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ 834 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ 859 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i)); 875 WRITE_REG32(ha, Q81_CTL_XGMAC_ADDR, (reg | Q81_XGMAC_ADDR_R)); 1235 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ 1248 WRITE_REG32(h [all...] |
H A D | qls_isr.c | 362 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, Q81_CTL_HCS_CMD_CLR_RTH_INTR);
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H A D | qls_hw.h | 927 #define WRITE_REG32(ha, reg, val) bus_write_4((ha->pci_reg), reg, val) macro 934 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRE_MASK_VALUE | idx)) 941 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRD_MASK_VALUE | idx))
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/freebsd-12-stable/sys/dev/qlxgb/ |
H A D | qla_hw.h | 803 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->rds_rsp[i].producer_reg +\ 807 WRITE_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000), val) 810 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->sds_rsp[i].consumer_reg +\ 815 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F0, 0xFFFFFFFF);\ 817 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F1, 0xFFFFFFFF);\ 824 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x1);\ 831 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x0);\
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H A D | qla_reg.h | 236 #define WRITE_REG32(ha, reg, val) \ macro
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/freebsd-12-stable/sys/dev/qlxgbe/ |
H A D | ql_inline.h | 68 WRITE_REG32(ha, id_reg, id_val);
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H A D | ql_misc.c | 72 WRITE_REG32(ha, wnd_reg, addr); 89 WRITE_REG32(ha, Q8_WILD_CARD, *val); 1322 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0); 1330 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0x12345678); 1402 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0); 1410 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0x12345678);
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H A D | ql_isr.c | 802 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0); 920 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0); 921 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
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H A D | ql_ioctl.c | 123 WRITE_REG32(ha, u.rv->reg, u.rv->val);
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H A D | ql_hw.h | 207 #define WRITE_REG32(ha, reg, val) \ macro 1733 WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val)
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H A D | ql_hw.c | 1450 WRITE_REG32(ha, (Q8_HOST_MBOX0 + (i << 2)), *h_mbox); 1454 WRITE_REG32(ha, Q8_HOST_MBOX_CNTRL, 0x1); 1499 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0); 1500 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); 2918 WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2); 2919 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
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Completed in 201 milliseconds