• Home
  • History
  • Annotate
  • Raw
  • Download
  • only in /freebsd-12-stable/sys/dev/qlxge/

Lines Matching refs:WRITE_REG32

271 	WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
272 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower);
281 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
282 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_upper);
291 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
297 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, value);
336 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
337 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower);
347 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
348 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_upper);
392 WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, index);
393 WRITE_REG32(ha, Q81_CTL_ROUTING_DATA, data);
810 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, value);
813 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, value);
850 WRITE_REG32(ha, Q81_CTL_SYSTEM, value);
854 WRITE_REG32(ha, Q81_CTL_NIC_RCV_CONFIG, value);
869 WRITE_REG32(ha, Q81_CTL_FUNC_SPECIFIC, value);
875 WRITE_REG32(ha, Q81_CTL_INTR_MASK, value);
922 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, value);
928 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, value);
1039 WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_LO, value);
1042 WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_HI, value);
1049 WRITE_REG32(ha, Q81_CTL_CONFIG, value);
1118 WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_LO, value);
1121 WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_HI, value);
1128 WRITE_REG32(ha, Q81_CTL_CONFIG, value);
1188 WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_LO, value);
1191 WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_HI, value);
1198 WRITE_REG32(ha, Q81_CTL_CONFIG, value);
1821 WRITE_REG32(ha, Q81_CTL_FLASH_ADDR, (addr | Q81_CTL_FLASH_ADDR_R));
1918 WRITE_REG32(ha, Q81_CTL_SEMAPHORE, (mask|value));
1935 WRITE_REG32(ha, Q81_CTL_SEMAPHORE, mask);
1978 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, value);
2003 WRITE_REG32(ha, Q81_CTL_PROC_DATA, data);
2007 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, value);
2026 WRITE_REG32(ha, Q81_CTL_RESET, data);
2206 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, Q81_CTL_HCS_CMD_SET_HTR_INTR);
2246 WRITE_REG32(ha,\
2266 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS,\
2426 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS,\
2433 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS,\