Searched refs:Op5 (Results 1 - 5 of 5) sorted by relevance
/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local 653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); 660 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); 682 unsigned Op1, Op2, Op3, Op4, Op5; local 687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); 695 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandPredSpillCode.cpp | 148 MachineOperand &Op5 = MI->getOperand(5); local 158 NewMI->addOperand(Op5);
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 5416 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); local 5421 (Op5.isReg() && Op5.getReg() == ARM::PC); 5424 (Op5.isReg() && Op5.getReg() == ARM::SP)) && 5426 Op5.isImm() && !Op5.isImm0_508s4()); 5445 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially 5447 const ARMOperand *LastOp = &Op5; 5449 if (!Transform && Op5 [all...] |
/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAG.h | 924 SDValue Op3, SDValue Op4, SDValue Op5);
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 5789 SDValue Op3, SDValue Op4, SDValue Op5) { 5790 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 5788 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) argument
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