/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetOpcodes.h | 28 /// Check whether the given Opcode is a generic opcode that is not supposed 30 inline bool isPreISelGenericOpcode(unsigned Opcode) { argument 31 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START && 32 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; 35 /// Check whether the given Opcode is a target-specific opcode. 36 inline bool isTargetSpecificOpcode(unsigned Opcode) { argument 37 return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END;
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/freebsd-11-stable/contrib/llvm-project/lldb/source/Core/ |
H A D | Opcode.cpp | 1 //===-- Opcode.cpp ----------------------------------------------*- C++ -*-===// 9 #include "lldb/Core/Opcode.h" 24 int Opcode::Dump(Stream *s, uint32_t min_byte_width) { 27 case Opcode::eTypeInvalid: 30 case Opcode::eType8: 33 case Opcode::eType16: 36 case Opcode::eType16_2: 37 case Opcode::eType32: 41 case Opcode::eType64: 45 case Opcode [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
H A D | MCInstrInfo.h | 44 const MCInstrDesc &get(unsigned Opcode) const { 45 assert(Opcode < NumOpcodes && "Invalid opcode!"); 46 return Desc[Opcode]; 50 StringRef getName(unsigned Opcode) const { 51 assert(Opcode < NumOpcodes && "Invalid opcode!"); 52 return StringRef(&InstrNameData[InstrNameIndices[Opcode]]);
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H A D | MCInstBuilder.h | 26 MCInstBuilder(unsigned Opcode) { argument 27 Inst.setOpcode(Opcode);
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/freebsd-11-stable/contrib/llvm-project/lldb/include/lldb/Core/ |
H A D | Opcode.h | 1 //===-- Opcode.h ------------------------------------------------*- C++ -*-===// 29 class Opcode { class in namespace:lldb_private 41 Opcode() : m_byte_order(lldb::eByteOrderInvalid), m_type(eTypeInvalid) {} function in class:lldb_private::Opcode 43 Opcode(uint8_t inst, lldb::ByteOrder order) function in class:lldb_private::Opcode 48 Opcode(uint16_t inst, lldb::ByteOrder order) function in class:lldb_private::Opcode 53 Opcode(uint32_t inst, lldb::ByteOrder order) function in class:lldb_private::Opcode 58 Opcode(uint64_t inst, lldb::ByteOrder order) function in class:lldb_private::Opcode 63 Opcode(uint8_t *bytes, size_t length) function in class:lldb_private::Opcode 70 m_type = Opcode::eTypeInvalid; 73 Opcode [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCPredicates.h | 70 Predicate InvertPredicate(Predicate Opcode); 74 Predicate getSwappedPredicate(Predicate Opcode); 77 inline unsigned getPredicateCondition(Predicate Opcode) { argument 78 return (unsigned)(Opcode & ~BR_HINT_MASK); 82 inline unsigned getPredicateHint(Predicate Opcode) { argument 83 return (unsigned)(Opcode & BR_HINT_MASK);
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/freebsd-11-stable/contrib/llvm-project/clang/lib/AST/Interp/ |
H A D | Opcode.h | 1 //===--- Opcode.h - Opcodes for the constexpr VM ----------------*- C++ -*-===// 21 enum Opcode : uint32_t {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMUnwindOpAsm.h | 72 void EmitInt8(unsigned Opcode) { argument 73 Ops.push_back(Opcode & 0xff); 77 void EmitInt16(unsigned Opcode) { argument 78 Ops.push_back((Opcode >> 8) & 0xff); 79 Ops.push_back(Opcode & 0xff); 83 void EmitBytes(const uint8_t *Opcode, size_t Size) { argument 84 Ops.insert(Ops.end(), Opcode, Opcode + Size);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.h | 66 static BranchPredicate getBranchPredicate(unsigned Opcode); 95 unsigned Opcode) const; 99 unsigned Opcode) const; 102 MachineInstr &Inst, unsigned Opcode) const; 108 unsigned Opcode, 337 bool isSALU(uint16_t Opcode) const { 338 return get(Opcode).TSFlags & SIInstrFlags::SALU; 345 bool isVALU(uint16_t Opcode) const { 346 return get(Opcode).TSFlags & SIInstrFlags::VALU; 353 bool isVMEM(uint16_t Opcode) cons 809 getOpSize(uint16_t Opcode, unsigned OpNo) const argument [all...] |
H A D | R600InstrInfo.h | 84 /// \returns true if this \p Opcode represents an ALU instruction. 85 bool isALUInstr(unsigned Opcode) const; 86 bool hasInstrModifiers(unsigned Opcode) const; 87 bool isLDSInstr(unsigned Opcode) const; 88 bool isLDSRetInstr(unsigned Opcode) const; 90 /// \returns true if this \p Opcode represents an ALU instruction or an 94 bool isTransOnly(unsigned Opcode) const; 96 bool isVectorOnly(unsigned Opcode) const; 98 bool isExport(unsigned Opcode) const; 100 bool usesVertexCache(unsigned Opcode) cons [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFMISimplifyPatchable.cpp | 68 unsigned Opcode); 106 unsigned Opcode = DefInst->getOpcode(); local 108 if (Opcode == BPF::LDB || Opcode == BPF::LDH || Opcode == BPF::LDW || 109 Opcode == BPF::LDD || Opcode == BPF::STB || Opcode == BPF::STH || 110 Opcode == BPF::STW || Opcode 142 checkShift(MachineRegisterInfo *MRI, MachineBasicBlock &MBB, MachineOperand *RelocOp, const GlobalValue *GVal, unsigned Opcode) argument 173 unsigned Opcode = I->getParent()->getOpcode(); local 228 unsigned Opcode = Inst->getOpcode(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandImm.h | 23 unsigned Opcode; member in struct:llvm::AArch64_IMM::ImmInsnModel
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyTargetTransformInfo.cpp | 47 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, 53 Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo); 56 switch (Opcode) { 67 getArithmeticInstrCost(Opcode, VTy->getElementType()) + 75 unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, argument 77 unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index); 46 getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, const Instruction *CxtI) argument
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/freebsd-11-stable/sys/contrib/dev/acpica/components/parser/ |
H A D | psutils.c | 197 * Opcode - Opcode to store in the Op 208 UINT16 Opcode) 214 Op->Common.AmlOpcode = Opcode; 217 (AcpiPsGetOpcodeInfo (Opcode))->Name, 226 * PARAMETERS: Opcode - Opcode that will be stored in the new Op 239 UINT16 Opcode, 250 OpInfo = AcpiPsGetOpcodeInfo (Opcode); 262 else if (Opcode 206 AcpiPsInitOp( ACPI_PARSE_OBJECT *Op, UINT16 Opcode) argument 238 AcpiPsAllocOp( UINT16 Opcode, UINT8 *Aml) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | LeonPasses.cpp | 50 unsigned Opcode = MI.getOpcode(); local 51 if (Opcode >= SP::LDDArr && Opcode <= SP::LDrr) { 85 unsigned Opcode = MI.getOpcode(); local 86 if (Opcode == SP::CALL && MI.getNumOperands() > 0) { 137 unsigned Opcode = MI.getOpcode(); local 143 if (Opcode == SP::FSQRTD || Opcode == SP::FDIVD) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZTargetTransformInfo.cpp | 65 int SystemZTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, argument 78 switch (Opcode) { 351 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, 373 Opcode == Instruction::SDiv || Opcode == Instruction::SRem; 375 Opcode == Instruction::UDiv || Opcode == Instruction::URem; 402 if (Opcode == Instruction::Shl || Opcode == Instruction::LShr || 403 Opcode 350 getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, const Instruction *CxtI) argument 654 getBoolVecToIntConversionCost(unsigned Opcode, Type *Dst, const Instruction *I) argument 670 getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, const Instruction *I) argument 807 getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, const Instruction *I) argument 888 getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) argument 996 getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, const Instruction *I) argument 1061 getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond, bool UseMaskForGaps) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
H A D | Instruction.h | 148 static inline bool isUnaryOp(unsigned Opcode) { argument 149 return Opcode >= UnaryOpsBegin && Opcode < UnaryOpsEnd; 151 static inline bool isBinaryOp(unsigned Opcode) { argument 152 return Opcode >= BinaryOpsBegin && Opcode < BinaryOpsEnd; 155 static inline bool isIntDivRem(unsigned Opcode) { argument 156 return Opcode == UDiv || Opcode == SDiv || Opcode 160 isShift(unsigned Opcode) argument 175 isBitwiseLogicOp(unsigned Opcode) argument 486 isAssociative(unsigned Opcode) argument 499 isCommutative(unsigned Opcode) argument 517 isIdempotent(unsigned Opcode) argument 531 isNilpotent(unsigned Opcode) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonTargetTransformInfo.cpp | 154 unsigned HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, argument 158 assert(Opcode == Instruction::Load || Opcode == Instruction::Store); 159 if (Opcode == Instruction::Store) 160 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I); 198 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I); 201 unsigned HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, argument 203 return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace); 211 unsigned HexagonTTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *DataTy, argument 213 return BaseT::getGatherScatterOpCost(Opcode, DataT 217 getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond, bool UseMaskForGaps) argument 229 getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, const Instruction *I) argument 239 getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, const Instruction *CxtI) argument 253 getCastInstrCost(unsigned Opcode, Type *DstTy, Type *SrcTy, const Instruction *I) argument 266 getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) argument [all...] |
H A D | HexagonTargetTransformInfo.h | 115 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, 118 unsigned getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 122 unsigned getGatherScatterOpCost(unsigned Opcode, Type *DataTy, Value *Ptr, 124 unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 128 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 131 unsigned Opcode, Type *Ty, 138 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 140 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); 142 unsigned getCFInstrCost(unsigned Opcode) { argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCNaCl.h | 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetTransformInfo.cpp | 121 int PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, argument 124 return BaseT::getIntImmCostInst(Opcode, Idx, Imm, Ty); 135 switch (Opcode) { 277 unsigned Opcode = 0; local 312 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; 313 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; 314 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; 315 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; 316 case Intrinsic::rint: Opcode = ISD::FRINT; break; 317 case Intrinsic::lrint: Opcode 709 vectorCostAdjustment(int Cost, unsigned Opcode, Type *Ty1, Type *Ty2) argument 733 getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, const Instruction *CxtI) argument 762 getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, const Instruction *I) argument 770 getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, const Instruction *I) argument 776 getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) argument 849 getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, const Instruction *I) argument 922 getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond, bool UseMaskForGaps) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/tools/llvm-readobj/ |
H A D | ARMEHABIPrinter.h | 100 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 101 SW.startLine() << format("0x%02X ; vsp = vsp + %u\n", Opcode, 102 ((Opcode & 0x3f) << 2) + 4); 106 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 107 SW.startLine() << format("0x%02X ; vsp = vsp - %u\n", Opcode, 108 ((Opcode & 0x3f) << 2) + 4); 125 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 126 SW.startLine() << format("0x%02X ; reserved (ARM MOVrr)\n", Opcode); 130 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 131 SW.startLine() << format("0x%02X ; reserved (WiMMX MOVrr)\n", Opcode); 135 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 140 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 147 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 154 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 171 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 198 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 203 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 251 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 256 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 263 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 270 uint8_t Opcode = Opcodes[OI++ ^ 3]; local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86AvoidStoreForwardingBlocks.cpp | 132 static bool isXMMLoadOpcode(unsigned Opcode) { argument 133 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || 134 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || 135 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || 136 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || 137 Opcode 142 isYMMLoadOpcode(unsigned Opcode) argument 152 isPotentialBlockedMemCpyLd(unsigned Opcode) argument 208 isPotentialBlockingStoreInst(int Opcode, int LoadOpcode) argument [all...] |
H A D | X86TargetTransformInfo.h | 123 unsigned Opcode, Type *Ty, 131 int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 133 int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 135 int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); 136 int getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, 138 int getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 140 int getGatherScatterOpCost(unsigned Opcode, Type *DataTy, Value *Ptr, 154 int getArithmeticReductionCost(unsigned Opcode, Type *Ty, 160 int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 165 int getInterleavedMemoryOpCostAVX512(unsigned Opcode, Typ [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
H A D | AVRInstPrinter.cpp | 38 unsigned Opcode = MI->getOpcode(); local 43 switch (Opcode) { 51 if (Opcode == AVR::LDRdPtrPd) 56 if (Opcode == AVR::LDRdPtrPi) 69 if (Opcode == AVR::STPtrPdRr) 74 if (Opcode == AVR::STPtrPiRr)
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