/freebsd-10.1-release/contrib/llvm/lib/Target/R600/ |
H A D | R600ExpandSpecialInstrs.cpp | 34 const R600InstrInfo *TII; member in class:__anon2574::R600ExpandSpecialInstrsPass 41 TII(0) { } 59 TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo()); 61 const R600RegisterInfo &TRI = TII->getRegisterInfo(); 72 if (TII->isLDSRetInstr(MI.getOpcode())) { 73 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); 76 MachineInstr *Mov = TII->buildMovInstr(&MBB, I, 79 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(), 81 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(), 95 MachineInstr *PredSet = TII [all...] |
H A D | R600EmitClauseMarkers.cpp | 34 const R600InstrInfo *TII; member in class:__anon2573::R600EmitClauseMarkersPass 52 if (TII->isLDSRetInstr(MI->getOpcode())) 55 if(TII->isVector(*MI) || 56 TII->isCubeOp(MI->getOpcode()) || 57 TII->isReductionOp(MI->getOpcode())) 71 if (TII->isALUInstr(MI->getOpcode())) 73 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode())) 118 if (!TII->isALUInstr(MI->getOpcode()) && MI->getOpcode() != AMDGPU::DOT_4) 122 TII [all...] |
H A D | R600Packetizer.cpp | 59 const R600InstrInfo *TII; member in class:__anon2576::R600PacketizerList 74 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) 86 if (TII->isPredicated(BI)) 88 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write); 91 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); 96 if (isTrans || TII->isTransOnly(BI)) { 138 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]); 152 TII (static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo())), 153 TRI(TII->getRegisterInfo()) { 170 if (TII 326 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo(); local [all...] |
H A D | R600ClauseMergePass.cpp | 46 const R600InstrInfo *TII; member in class:__anon2571::R600ClauseMergePass 75 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::COUNT)).getImm(); 81 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::Enabled)).getImm(); 86 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT); 105 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT); 109 if (CumuledInsts >= TII->getMaxAlusPerClause()) { 117 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE0); 119 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK0); 121 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR0); 133 TII [all...] |
H A D | AMDGPUConvertToISA.cpp | 49 const AMDGPUInstrInfo * TII = local 58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
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H A D | SILowerControlFlow.cpp | 70 const TargetInstrInfo *TII; member in class:__anon2585::SILowerControlFlowPass 94 MachineFunctionPass(ID), TRI(0), TII(0) { } 155 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ)) 174 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) 179 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP)) 191 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)); 200 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) 203 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) 219 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst) 222 BuildMI(MBB, &MI, DL, TII [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandPredSpillCode.cpp | 75 const HexagonInstrInfo *TII = QTM.getInstrInfo(); local 96 if (!TII->isValidOffset(Hexagon::STriw_indexed, Offset)) { 97 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) { 99 TII->get(Hexagon::CONST32_Int_Real), 101 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr), 104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), 107 TII->get(Hexagon::STriw_indexed)) 111 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri), 113 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), 116 TII [all...] |
H A D | HexagonSplitConst32AndConst64.cpp | 70 const TargetInstrInfo *TII = QTM.getInstrInfo(); local 87 TII->get(Hexagon::LO), DestReg).addOperand(Symbol); 89 TII->get(Hexagon::HI), DestReg).addOperand(Symbol); 100 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol); 102 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol); 113 TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol); 115 TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol); 126 TII->get(Hexagon::LOi), DestReg).addImm(ImmValue); 128 TII->get(Hexagon::HIi), DestReg).addImm(ImmValue); 145 TII [all...] |
H A D | HexagonRegisterInfo.cpp | 131 const HexagonInstrInfo &TII = local 146 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) && 147 !TII.isSpillPredRegOp(&MI)) { 154 if (!TII.isValidOffset(MI.getOpcode(), Offset)) { 176 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) { 178 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset); 180 TII.get(Hexagon::ADD_rr), 184 TII.get(Hexagon::ADD_ri), 205 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) { 207 TII [all...] |
H A D | HexagonSplitTFRCondSets.cpp | 82 const TargetInstrInfo *TII = QTM.getInstrInfo(); local 114 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1), 118 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc2), 134 TII->get(Hexagon::TFR_cPt), DestReg). 139 TII->get(Hexagon::TFRI_cNotPt), DestReg). 144 TII->get(Hexagon::TFRI_cNotPt_f), DestReg). 160 TII->get(Hexagon::TFRI_cPt), DestReg). 165 TII->get(Hexagon::TFRI_cPt_f), DestReg). 174 TII->get(Hexagon::TFR_cNotPt), DestReg). 190 TII [all...] |
H A D | HexagonFrameLowering.cpp | 118 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 122 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0); 125 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real), 127 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr), 132 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes); 157 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 161 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME)); 162 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::ADD_rr), 183 BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4)); 198 BuildMI(MBB, MBBI, dl, TII 228 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local 283 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 49 const ARMBaseInstrInfo &TII = local 55 !(TII.getSubtarget().isLikeA9() && 65 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && 66 (TII.canCauseFpMLxStall(MI->getOpcode()) || 67 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
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H A D | Thumb1FrameLowering.cpp | 39 const TargetInstrInfo &TII, DebugLoc dl, 42 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, 50 const Thumb1InstrInfo &TII = local 71 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); 74 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); 88 const Thumb1InstrInfo &TII = local 109 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, 114 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, 176 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) 187 emitSPUpdate(MBB, MBBI, TII, d 37 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, DebugLoc dl, const Thumb1RegisterInfo &MRI, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) argument 245 const Thumb1InstrInfo &TII = local 336 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 375 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local [all...] |
H A D | Thumb2RegisterInfo.cpp | 42 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 48 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
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/freebsd-10.1-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.cpp | 45 const MSP430InstrInfo &TII = local 66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) 70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW) 98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW) 110 const MSP430InstrInfo &TII = local 135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW); 157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW); 161 TII.get(MSP430::SUB16ri), MSP430::SPW) 170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW) 191 const TargetInstrInfo &TII local 217 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 228 const MSP430InstrInfo &TII = local [all...] |
H A D | MSP430BranchSelector.cpp | 55 const MSP430InstrInfo *TII = local 70 BlockSize += TII->GetInstSizeInBytes(MBBI); 107 MBBStartOffset += TII->GetInstSizeInBytes(I); 154 TII->ReverseBranchCondition(Cond); 155 BuildMI(MBB, I, dl, TII->get(MSP430::JCC)) 161 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest);
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/freebsd-10.1-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCBranchSelector.cpp | 65 const PPCInstrInfo *TII = local 80 BlockSize += TII->GetInstSizeInBytes(MBBI); 124 MBBStartOffset += TII->GetInstSizeInBytes(I); 167 BuildMI(MBB, I, dl, TII->get(PPC::BCC)) 170 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2); 172 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2); 174 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2); 176 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2); 182 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
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/freebsd-10.1-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 66 const SystemZInstrInfo &TII = local 87 unsigned OpcodeForOffset = TII.getOpcodeForOffset(Opcode, Offset); 97 OpcodeForOffset = TII.getOpcodeForOffset(Opcode, Offset); 110 TII.loadImmediate(MBB, MI, ScratchReg, HighOffset); 116 unsigned LAOpcode = TII.getOpcodeForOffset(SystemZ::LA, HighOffset); 118 BuildMI(MBB, MI, DL, TII.get(LAOpcode),ScratchReg) 123 TII.loadImmediate(MBB, MI, ScratchReg, HighOffset); 124 BuildMI(MBB, MI, DL, TII.get(SystemZ::AGR),ScratchReg) 133 MI->setDesc(TII.get(OpcodeForOffset));
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/freebsd-10.1-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsLongBranch.cpp | 173 const MipsInstrInfo *TII = local 181 MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI); 220 const MipsInstrInfo *TII = local 222 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); 223 const MCInstrDesc &NewDesc = TII->get(NewOpc); 257 const MipsInstrInfo *TII = local 293 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) 295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) 299 .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB)) 300 .append(BuildMI(*MF, DL, TII 400 emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) argument 412 const MipsInstrInfo *TII = local [all...] |
H A D | Mips16RegisterInfo.cpp | 68 const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo(); local 69 TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true); 70 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true); 142 const Mips16InstrInfo &TII = local 145 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
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/freebsd-10.1-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | TargetSchedule.h | 38 const TargetInstrInfo *TII; member in class:llvm::TargetSchedModel 44 TargetSchedModel(): STI(0), TII(0) {} 58 const TargetInstrInfo *getInstrInfo() const { return TII; } 157 /// present this method falls back to TII->getInstrLatency with an empty
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/freebsd-10.1-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcRegisterInfo.cpp | 111 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 120 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1) 125 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) 138 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1) 140 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1) 143 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) 177 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 182 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri)) 185 MI.setDesc(TII.get(SP::STDFri)); 189 const TargetInstrInfo &TII local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 115 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 172 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) 177 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) 183 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) 193 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) 198 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) 204 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) 222 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) 227 BuildMI(MBB, II, dl, TII.get(NewOpcode)) 233 BuildMI(MBB, II, dl, TII 253 const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo(); local [all...] |
H A D | XCoreFrameLowering.cpp | 44 const TargetInstrInfo &TII) { 51 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg) 59 const TargetInstrInfo &TII) { 66 BuildMI(MBB, I, dl, TII.get(Opcode)) 92 const XCoreInstrInfo &TII = local 105 loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII); 133 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize); 138 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel); 149 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII); 154 BuildMI(MBB, MBBI, dl, TII 41 loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DstReg, int Offset, DebugLoc dl, const TargetInstrInfo &TII) argument 56 storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, int Offset, DebugLoc dl, const TargetInstrInfo &TII) argument 206 const XCoreInstrInfo &TII = local 275 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local 306 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local 337 const XCoreInstrInfo &TII = local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 149 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) { 174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) 186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), 189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) 394 const X86InstrInfo &TII = *TM.getInstrInfo(); 455 TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)), 498 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) 505 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)) 521 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) 528 BuildMI(MBB, MBBI, DL, TII 146 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned StackPtr, int64_t NumBytes, bool Is64Bit, bool IsLP64, bool UseLEA, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) argument [all...] |