Target/R600/R600ExpandSpecialInstrs.cpp

34   const R600InstrInfo *TII;
41     TII(0) { }
59   TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
61   const R600RegisterInfo &TRI = TII->getRegisterInfo();
72       if (TII->isLDSRetInstr(MI.getOpcode())) {
73         int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
76         MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
79         int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(),
81         int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(),
95         MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
100         TII->addFlag(PredSet, 0, MO_FLAG_MASK);
102           TII->setImmOperand(PredSet, AMDGPU::OpName::update_exec_mask, 1);
104           TII->setImmOperand(PredSet, AMDGPU::OpName::update_pred, 1);
123           BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_XY,
130             TII->addFlag(BMI, 0, MO_FLAG_MASK);
132             TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
152           BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_ZW,
159             TII->addFlag(BMI, 0, MO_FLAG_MASK);
161             TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
169         const R600RegisterInfo &TRI = TII->getRegisterInfo();
176           BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_LOAD_P0,
182             TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
190         const R600RegisterInfo &TRI = TII->getRegisterInfo();
200               TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg);
205             TII->addFlag(BMI, 0, MO_FLAG_MASK);
208             TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
213               TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
216               TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
229       bool IsReduction = TII->isReductionOp(MI.getOpcode());
230       bool IsVector = TII->isVector(MI);
231       bool IsCube = TII->isCubeOp(MI.getOpcode());
263                             TII->getOperandIdx(MI, AMDGPU::OpName::dst)).getReg();
265                            TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg();
270           int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1);
318           TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
323           TII->addFlag(NewMI, 0, MO_FLAG_MASK);
326           TII->addFlag(NewMI, 0, MO_FLAG_NOT_LAST);