Searched refs:MIb (Results 1 - 21 of 21) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ControlFlowFinalizer.cpp351 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), local
355 return ClauseFile(MIb, std::move(ClauseContent));
570 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable
575 Pair.second.insert(MIb);
595 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable
599 IfThenElseStack.push_back(MIb);
600 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
609 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable
613 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
614 IfThenElseStack.push_back(MIb);
624 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable
628 (void)MIb; variable
643 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable
651 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable
[all...]
H A DSIInstrInfo.cpp2782 const MachineInstr &MIb) const {
2789 !getMemOperandsWithOffsetWidth(MIb, BaseOps1, Offset1, Offset1IsScalable,
2796 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) {
2801 unsigned Width1 = MIb.memoperands().front()->getSize();
2806 const MachineInstr &MIb) const {
2809 assert(MIb.mayLoadOrStore() &&
2810 "MIb must load from or modify a memory location");
2812 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects())
2816 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
2825 if (isDS(MIb))
[all...]
H A DSIInstrInfo.h136 const MachineInstr &MIb) const;
322 const MachineInstr &MIb) const override;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp578 MCInst const &MIb, bool ExtendedB,
586 unsigned Opcode = MIb.getOpcode();
591 MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb);
600 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb);
614 if (MIb.getOpcode() == Hexagon::S2_allocframe)
619 // Note that MIb (slot1) can be extended and MIa (slot0)
626 if (subInstWouldBeExtended(MIb) && !ExtendedB)
630 // If jumpr r31 appears, it must be in slot 0, and never slot 1 (MIb).
632 if ((MIb.getNumOperands() > 1) && MIb
576 isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, bool ExtendedA, MCInst const &MIb, bool ExtendedB, bool bisReversable, MCSubtargetInfo const &STI) argument
655 isDuplexPair(MCInst const &MIa, MCInst const &MIb) argument
[all...]
H A DHexagonMCCompound.cpp335 MCInst const &MIb, bool IsExtendedB) {
337 unsigned MIbG = getCompoundCandidateGroup(MIb, IsExtendedB);
345 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg()));
334 isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, MCInst const &MIb, bool IsExtendedB) argument
H A DHexagonMCInstrInfo.h231 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
268 bool ExtendedA, MCInst const &MIb, bool ExtendedB,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.h39 const MachineInstr &MIb) const override;
H A DLanaiInstrInfo.cpp89 const MachineInstr &MIa, const MachineInstr &MIb) const {
91 assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
93 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
94 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
107 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h95 const MachineInstr &MIb) const override;
H A DRISCVInstrInfo.cpp607 const MachineInstr &MIa, const MachineInstr &MIb) const {
609 assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
611 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
612 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
625 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h292 const MachineInstr &MIb) const override;
357 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
H A DHexagonInstrInfo.cpp1898 const MachineInstr &MIa, const MachineInstr &MIb) const {
1899 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1900 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
1905 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1916 // Get the base register in MIb.
1918 if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1920 const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1929 unsigned SizeB = getMemAccessSize(MIb);
1933 const MachineOperand &OffB = MIb
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h357 const MachineInstr &MIb) const override;
H A DSystemZInstrInfo.cpp1961 const MachineInstr &MIb) const {
1963 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
1971 MachineMemOperand *MMOb = *MIb.memoperands_begin();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h60 const MachineInstr &MIb) const override;
H A DAArch64LoadStoreOptimizer.cpp1150 for (MachineInstr *MIb : MemInsns)
1151 if (MIa.mayAlias(AA, *MIb, /*UseTBAA*/ false))
H A DAArch64InstrInfo.cpp968 const MachineInstr &MIa, const MachineInstr &MIb) const {
976 assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
978 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
979 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
991 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, OffsetBIsScalable,
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1675 const MachineInstr &MIb) const {
1678 assert(MIb.mayLoadOrStore() &&
1679 "MIb must load from or modify a memory location");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h504 const MachineInstr &MIb) const override;
H A DPPCInstrInfo.cpp4662 const MachineInstr &MIa, const MachineInstr &MIb) const {
4664 assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
4666 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
4667 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
4680 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
/freebsd-13-stable/sys/cddl/dev/dtrace/x86/
H A Ddis_tables.c153 MIb, /* for 386 logicals */ enumerator in enum:__anon8768
557 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb),
3957 case MIb:

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