Searched refs:pfifo (Results 1 - 25 of 29) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-netx/
H A DMakefile7 obj-y += time.o generic.o pfifo.o xc.o
H A Dpfifo.c2 * arch/arm/mach-netx/pfifo.c
27 #include <mach/pfifo.h>
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-netx/
H A DMakefile7 obj-y += time.o generic.o pfifo.o xc.o
H A Dpfifo.c2 * arch/arm/mach-netx/pfifo.c
27 #include <mach/pfifo.h>
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/gpu/drm/nouveau/
H A Dnouveau_channel.c120 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
133 for (channel = 0; channel < pfifo->channels; channel++) {
139 if (channel == pfifo->channels)
212 pfifo->reassign(dev, false);
222 ret = pfifo->create_context(chan);
228 pfifo->reassign(dev, true);
252 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
281 /* This will prevent pfifo from switching channels. */
282 pfifo->reassign(dev, false);
299 if (pfifo
[all...]
H A Dnv50_fifo.c35 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
41 cur = pfifo->playlist[pfifo->cur_playlist];
42 pfifo->cur_playlist = !pfifo->cur_playlist;
156 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
161 if (pfifo->playlist[0]) {
162 pfifo->cur_playlist = !pfifo->cur_playlist;
168 &pfifo
199 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
385 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
[all...]
H A Dnv04_fifo.c208 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
213 chid = pfifo->channel_id(dev);
233 nv04_fifo_do_load_context(dev, pfifo->channels - 1);
234 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
284 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
290 nv04_fifo_do_load_context(dev, pfifo->channels - 1);
291 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
294 pfifo->enable(dev);
295 pfifo->reassign(dev, true);
H A Dnv10_fifo.c143 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
147 chid = pfifo->channel_id(dev);
174 nv10_fifo_do_load_context(dev, pfifo->channels - 1);
175 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
228 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
234 nv10_fifo_do_load_context(dev, pfifo->channels - 1);
235 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
238 pfifo->enable(dev);
239 pfifo->reassign(dev, true);
H A Dnv40_fifo.c154 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
158 chid = pfifo->channel_id(dev);
192 nv40_fifo_do_load_context(dev, pfifo->channels - 1);
194 NV40_PFIFO_CACHE1_PUSH1_DMA | (pfifo->channels - 1));
285 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
291 nv40_fifo_do_load_context(dev, pfifo->channels - 1);
292 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
295 pfifo->enable(dev);
296 pfifo->reassign(dev, true);
H A Dnouveau_drv.c146 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
179 for (i = 0; i < pfifo->channels; i++) {
201 pfifo->reassign(dev, false);
202 pfifo->disable(dev);
203 pfifo->unload_context(dev);
235 pfifo->enable(dev);
236 pfifo->reassign(dev, true);
H A Dnouveau_mem.c47 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
57 if (!pfifo->cache_flush(dev))
60 pfifo->reassign(dev, false);
61 pfifo->cache_flush(dev);
62 pfifo->cache_pull(dev, false);
69 pfifo->cache_pull(dev, true);
70 pfifo->reassign(dev, true);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/gpu/drm/nouveau/
H A Dnouveau_channel.c120 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
133 for (channel = 0; channel < pfifo->channels; channel++) {
139 if (channel == pfifo->channels)
212 pfifo->reassign(dev, false);
222 ret = pfifo->create_context(chan);
228 pfifo->reassign(dev, true);
252 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
281 /* This will prevent pfifo from switching channels. */
282 pfifo->reassign(dev, false);
299 if (pfifo
[all...]
H A Dnv50_fifo.c35 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
41 cur = pfifo->playlist[pfifo->cur_playlist];
42 pfifo->cur_playlist = !pfifo->cur_playlist;
156 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
161 if (pfifo->playlist[0]) {
162 pfifo->cur_playlist = !pfifo->cur_playlist;
168 &pfifo
199 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
385 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
[all...]
H A Dnv04_fifo.c208 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
213 chid = pfifo->channel_id(dev);
233 nv04_fifo_do_load_context(dev, pfifo->channels - 1);
234 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
284 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
290 nv04_fifo_do_load_context(dev, pfifo->channels - 1);
291 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
294 pfifo->enable(dev);
295 pfifo->reassign(dev, true);
H A Dnv10_fifo.c143 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
147 chid = pfifo->channel_id(dev);
174 nv10_fifo_do_load_context(dev, pfifo->channels - 1);
175 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
228 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
234 nv10_fifo_do_load_context(dev, pfifo->channels - 1);
235 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
238 pfifo->enable(dev);
239 pfifo->reassign(dev, true);
H A Dnv40_fifo.c154 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
158 chid = pfifo->channel_id(dev);
192 nv40_fifo_do_load_context(dev, pfifo->channels - 1);
194 NV40_PFIFO_CACHE1_PUSH1_DMA | (pfifo->channels - 1));
285 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
291 nv40_fifo_do_load_context(dev, pfifo->channels - 1);
292 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
295 pfifo->enable(dev);
296 pfifo->reassign(dev, true);
H A Dnouveau_drv.c146 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
179 for (i = 0; i < pfifo->channels; i++) {
201 pfifo->reassign(dev, false);
202 pfifo->disable(dev);
203 pfifo->unload_context(dev);
235 pfifo->enable(dev);
236 pfifo->reassign(dev, true);
H A Dnouveau_mem.c47 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; local
57 if (!pfifo->cache_flush(dev))
60 pfifo->reassign(dev, false);
61 pfifo->cache_flush(dev);
62 pfifo->cache_pull(dev, false);
69 pfifo->cache_pull(dev, true);
70 pfifo->reassign(dev, true);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-netx/include/mach/
H A Dnetx-regs.h320 #define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
321 #define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
327 #define NETX_PFIFO_FILL_LEVEL(pfifo) NETX_PFIFO_REG(0x180 + ((pfifo)<<2))
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-netx/include/mach/
H A Dnetx-regs.h320 #define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
321 #define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
327 #define NETX_PFIFO_FILL_LEVEL(pfifo) NETX_PFIFO_REG(0x180 + ((pfifo)<<2))
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/iproute2/
H A DMakefile55 ln -sf tc-pbfifo.8 $(DESTDIR)$(MANDIR)/man8/tc-pfifo.8
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/iproute2/
H A DMakefile55 ln -sf tc-pbfifo.8 $(DESTDIR)$(MANDIR)/man8/tc-pfifo.8
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/iproute2/
H A DMakefile55 ln -sf tc-pbfifo.8 $(DESTDIR)$(MANDIR)/man8/tc-pfifo.8
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/
H A Dnetx-eth.c34 #include <mach/pfifo.h>
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/
H A Dnetx-eth.c34 #include <mach/pfifo.h>

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