1/* 2 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 * Copyright 2005 Stephane Marchesin 4 * 5 * The Weather Channel (TM) funded Tungsten Graphics to develop the 6 * initial release of the Radeon 8500 driver under the XFree86 license. 7 * This notice must be preserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the next 17 * paragraph) shall be included in all copies or substantial portions of the 18 * Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 * 28 * Authors: 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 33#include "drmP.h" 34#include "drm.h" 35#include "drm_sarea.h" 36#include "nouveau_drv.h" 37 38/* 39 * NV10-NV40 tiling helpers 40 */ 41 42static void 43nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, 44 uint32_t size, uint32_t pitch) 45{ 46 struct drm_nouveau_private *dev_priv = dev->dev_private; 47 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; 48 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; 49 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 50 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 51 52 tile->addr = addr; 53 tile->size = size; 54 tile->used = !!pitch; 55 nouveau_fence_unref((void **)&tile->fence); 56 57 if (!pfifo->cache_flush(dev)) 58 return; 59 60 pfifo->reassign(dev, false); 61 pfifo->cache_flush(dev); 62 pfifo->cache_pull(dev, false); 63 64 nouveau_wait_for_idle(dev); 65 66 pgraph->set_region_tiling(dev, i, addr, size, pitch); 67 pfb->set_region_tiling(dev, i, addr, size, pitch); 68 69 pfifo->cache_pull(dev, true); 70 pfifo->reassign(dev, true); 71} 72 73struct nouveau_tile_reg * 74nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size, 75 uint32_t pitch) 76{ 77 struct drm_nouveau_private *dev_priv = dev->dev_private; 78 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; 79 struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL; 80 int i; 81 82 spin_lock(&dev_priv->tile.lock); 83 84 for (i = 0; i < pfb->num_tiles; i++) { 85 if (tile[i].used) 86 /* Tile region in use. */ 87 continue; 88 89 if (tile[i].fence && 90 !nouveau_fence_signalled(tile[i].fence, NULL)) 91 /* Pending tile region. */ 92 continue; 93 94 if (max(tile[i].addr, addr) < 95 min(tile[i].addr + tile[i].size, addr + size)) 96 /* Kill an intersecting tile region. */ 97 nv10_mem_set_region_tiling(dev, i, 0, 0, 0); 98 99 if (pitch && !found) { 100 /* Free tile region. */ 101 nv10_mem_set_region_tiling(dev, i, addr, size, pitch); 102 found = &tile[i]; 103 } 104 } 105 106 spin_unlock(&dev_priv->tile.lock); 107 108 return found; 109} 110 111void 112nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile, 113 struct nouveau_fence *fence) 114{ 115 if (fence) { 116 /* Mark it as pending. */ 117 tile->fence = fence; 118 nouveau_fence_ref(fence); 119 } 120 121 tile->used = false; 122} 123 124/* 125 * NV50 VM helpers 126 */ 127int 128nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size, 129 uint32_t flags, uint64_t phys) 130{ 131 struct drm_nouveau_private *dev_priv = dev->dev_private; 132 struct nouveau_gpuobj *pgt; 133 unsigned block; 134 int i; 135 136 virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1; 137 size = (size >> 16) << 1; 138 139 phys |= ((uint64_t)flags << 32); 140 phys |= 1; 141 if (dev_priv->vram_sys_base) { 142 phys += dev_priv->vram_sys_base; 143 phys |= 0x30; 144 } 145 146 while (size) { 147 unsigned offset_h = upper_32_bits(phys); 148 unsigned offset_l = lower_32_bits(phys); 149 unsigned pte, end; 150 151 for (i = 7; i >= 0; i--) { 152 block = 1 << (i + 1); 153 if (size >= block && !(virt & (block - 1))) 154 break; 155 } 156 offset_l |= (i << 7); 157 158 phys += block << 15; 159 size -= block; 160 161 while (block) { 162 pgt = dev_priv->vm_vram_pt[virt >> 14]; 163 pte = virt & 0x3ffe; 164 165 end = pte + block; 166 if (end > 16384) 167 end = 16384; 168 block -= (end - pte); 169 virt += (end - pte); 170 171 while (pte < end) { 172 nv_wo32(dev, pgt, pte++, offset_l); 173 nv_wo32(dev, pgt, pte++, offset_h); 174 } 175 } 176 } 177 dev_priv->engine.instmem.flush(dev); 178 179 nv50_vm_flush(dev, 5); 180 nv50_vm_flush(dev, 0); 181 nv50_vm_flush(dev, 4); 182 nv50_vm_flush(dev, 6); 183 return 0; 184} 185 186void 187nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size) 188{ 189 struct drm_nouveau_private *dev_priv = dev->dev_private; 190 struct nouveau_gpuobj *pgt; 191 unsigned pages, pte, end; 192 193 virt -= dev_priv->vm_vram_base; 194 pages = (size >> 16) << 1; 195 196 while (pages) { 197 pgt = dev_priv->vm_vram_pt[virt >> 29]; 198 pte = (virt & 0x1ffe0000ULL) >> 15; 199 200 end = pte + pages; 201 if (end > 16384) 202 end = 16384; 203 pages -= (end - pte); 204 virt += (end - pte) << 15; 205 206 while (pte < end) 207 nv_wo32(dev, pgt, pte++, 0); 208 } 209 dev_priv->engine.instmem.flush(dev); 210 211 nv50_vm_flush(dev, 5); 212 nv50_vm_flush(dev, 0); 213 nv50_vm_flush(dev, 4); 214 nv50_vm_flush(dev, 6); 215} 216 217/* 218 * Cleanup everything 219 */ 220void 221nouveau_mem_close(struct drm_device *dev) 222{ 223 struct drm_nouveau_private *dev_priv = dev->dev_private; 224 225 nouveau_bo_unpin(dev_priv->vga_ram); 226 nouveau_bo_ref(NULL, &dev_priv->vga_ram); 227 228 ttm_bo_device_release(&dev_priv->ttm.bdev); 229 230 nouveau_ttm_global_release(dev_priv); 231 232 if (drm_core_has_AGP(dev) && dev->agp) { 233 struct drm_agp_mem *entry, *tempe; 234 235 /* Remove AGP resources, but leave dev->agp 236 intact until drv_cleanup is called. */ 237 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) { 238 if (entry->bound) 239 drm_unbind_agp(entry->memory); 240 drm_free_agp(entry->memory, entry->pages); 241 kfree(entry); 242 } 243 INIT_LIST_HEAD(&dev->agp->memory); 244 245 if (dev->agp->acquired) 246 drm_agp_release(dev); 247 248 dev->agp->acquired = 0; 249 dev->agp->enabled = 0; 250 } 251 252 if (dev_priv->fb_mtrr) { 253 drm_mtrr_del(dev_priv->fb_mtrr, 254 pci_resource_start(dev->pdev, 1), 255 pci_resource_len(dev->pdev, 1), DRM_MTRR_WC); 256 dev_priv->fb_mtrr = -1; 257 } 258} 259 260static uint32_t 261nouveau_mem_detect_nv04(struct drm_device *dev) 262{ 263 uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0); 264 265 if (boot0 & 0x00000100) 266 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024; 267 268 switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) { 269 case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB: 270 return 32 * 1024 * 1024; 271 case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB: 272 return 16 * 1024 * 1024; 273 case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB: 274 return 8 * 1024 * 1024; 275 case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB: 276 return 4 * 1024 * 1024; 277 } 278 279 return 0; 280} 281 282static uint32_t 283nouveau_mem_detect_nforce(struct drm_device *dev) 284{ 285 struct drm_nouveau_private *dev_priv = dev->dev_private; 286 struct pci_dev *bridge; 287 uint32_t mem; 288 289 bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1)); 290 if (!bridge) { 291 NV_ERROR(dev, "no bridge device\n"); 292 return 0; 293 } 294 295 if (dev_priv->flags & NV_NFORCE) { 296 pci_read_config_dword(bridge, 0x7C, &mem); 297 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; 298 } else 299 if (dev_priv->flags & NV_NFORCE2) { 300 pci_read_config_dword(bridge, 0x84, &mem); 301 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; 302 } 303 304 NV_ERROR(dev, "impossible!\n"); 305 return 0; 306} 307 308/* returns the amount of FB ram in bytes */ 309int 310nouveau_mem_detect(struct drm_device *dev) 311{ 312 struct drm_nouveau_private *dev_priv = dev->dev_private; 313 314 if (dev_priv->card_type == NV_04) { 315 dev_priv->vram_size = nouveau_mem_detect_nv04(dev); 316 } else 317 if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) { 318 dev_priv->vram_size = nouveau_mem_detect_nforce(dev); 319 } else 320 if (dev_priv->card_type < NV_50) { 321 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA); 322 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK; 323 } else 324 if (dev_priv->card_type < NV_C0) { 325 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA); 326 dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32; 327 dev_priv->vram_size &= 0xffffffff00ll; 328 if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac) { 329 dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10); 330 dev_priv->vram_sys_base <<= 12; 331 } 332 } else { 333 dev_priv->vram_size = nv_rd32(dev, 0x10f20c) << 20; 334 dev_priv->vram_size *= nv_rd32(dev, 0x121c74); 335 } 336 337 NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20)); 338 if (dev_priv->vram_sys_base) { 339 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n", 340 dev_priv->vram_sys_base); 341 } 342 343 if (dev_priv->vram_size) 344 return 0; 345 return -ENOMEM; 346} 347 348int 349nouveau_mem_reset_agp(struct drm_device *dev) 350{ 351#if __OS_HAS_AGP 352 uint32_t saved_pci_nv_1, pmc_enable; 353 int ret; 354 355 /* First of all, disable fast writes, otherwise if it's 356 * already enabled in the AGP bridge and we disable the card's 357 * AGP controller we might be locking ourselves out of it. */ 358 if (nv_rd32(dev, NV04_PBUS_PCI_NV_19) & PCI_AGP_COMMAND_FW) { 359 struct drm_agp_info info; 360 struct drm_agp_mode mode; 361 362 ret = drm_agp_info(dev, &info); 363 if (ret) 364 return ret; 365 366 mode.mode = info.mode & ~PCI_AGP_COMMAND_FW; 367 ret = drm_agp_enable(dev, mode); 368 if (ret) 369 return ret; 370 } 371 372 saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1); 373 374 /* clear busmaster bit */ 375 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4); 376 /* disable AGP */ 377 nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0); 378 379 /* power cycle pgraph, if enabled */ 380 pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE); 381 if (pmc_enable & NV_PMC_ENABLE_PGRAPH) { 382 nv_wr32(dev, NV03_PMC_ENABLE, 383 pmc_enable & ~NV_PMC_ENABLE_PGRAPH); 384 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | 385 NV_PMC_ENABLE_PGRAPH); 386 } 387 388 /* and restore (gives effect of resetting AGP) */ 389 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1); 390#endif 391 392 return 0; 393} 394 395int 396nouveau_mem_init_agp(struct drm_device *dev) 397{ 398#if __OS_HAS_AGP 399 struct drm_nouveau_private *dev_priv = dev->dev_private; 400 struct drm_agp_info info; 401 struct drm_agp_mode mode; 402 int ret; 403 404 if (!dev->agp->acquired) { 405 ret = drm_agp_acquire(dev); 406 if (ret) { 407 NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret); 408 return ret; 409 } 410 } 411 412 nouveau_mem_reset_agp(dev); 413 414 ret = drm_agp_info(dev, &info); 415 if (ret) { 416 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret); 417 return ret; 418 } 419 420 /* see agp.h for the AGPSTAT_* modes available */ 421 mode.mode = info.mode; 422 ret = drm_agp_enable(dev, mode); 423 if (ret) { 424 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret); 425 return ret; 426 } 427 428 dev_priv->gart_info.type = NOUVEAU_GART_AGP; 429 dev_priv->gart_info.aper_base = info.aperture_base; 430 dev_priv->gart_info.aper_size = info.aperture_size; 431#endif 432 return 0; 433} 434 435int 436nouveau_mem_init(struct drm_device *dev) 437{ 438 struct drm_nouveau_private *dev_priv = dev->dev_private; 439 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev; 440 int ret, dma_bits = 32; 441 442 dev_priv->fb_phys = pci_resource_start(dev->pdev, 1); 443 dev_priv->gart_info.type = NOUVEAU_GART_NONE; 444 445 if (dev_priv->card_type >= NV_50 && 446 pci_dma_supported(dev->pdev, DMA_BIT_MASK(40))) 447 dma_bits = 40; 448 449 ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits)); 450 if (ret) { 451 NV_ERROR(dev, "Error setting DMA mask: %d\n", ret); 452 return ret; 453 } 454 455 ret = nouveau_ttm_global_init(dev_priv); 456 if (ret) 457 return ret; 458 459 ret = ttm_bo_device_init(&dev_priv->ttm.bdev, 460 dev_priv->ttm.bo_global_ref.ref.object, 461 &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET, 462 dma_bits <= 32 ? true : false); 463 if (ret) { 464 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret); 465 return ret; 466 } 467 468 spin_lock_init(&dev_priv->tile.lock); 469 470 dev_priv->fb_available_size = dev_priv->vram_size; 471 dev_priv->fb_mappable_pages = dev_priv->fb_available_size; 472 if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1)) 473 dev_priv->fb_mappable_pages = 474 pci_resource_len(dev->pdev, 1); 475 dev_priv->fb_mappable_pages >>= PAGE_SHIFT; 476 477 /* remove reserved space at end of vram from available amount */ 478 dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram; 479 dev_priv->fb_aper_free = dev_priv->fb_available_size; 480 481 /* mappable vram */ 482 ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM, 483 dev_priv->fb_available_size >> PAGE_SHIFT); 484 if (ret) { 485 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret); 486 return ret; 487 } 488 489 ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM, 490 0, 0, true, true, &dev_priv->vga_ram); 491 if (ret == 0) 492 ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM); 493 if (ret) { 494 NV_WARN(dev, "failed to reserve VGA memory\n"); 495 nouveau_bo_ref(NULL, &dev_priv->vga_ram); 496 } 497 498 /* GART */ 499#if !defined(__powerpc__) && !defined(__ia64__) 500 if (drm_device_is_agp(dev) && dev->agp && !nouveau_noagp) { 501 ret = nouveau_mem_init_agp(dev); 502 if (ret) 503 NV_ERROR(dev, "Error initialising AGP: %d\n", ret); 504 } 505#endif 506 507 if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) { 508 ret = nouveau_sgdma_init(dev); 509 if (ret) { 510 NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret); 511 return ret; 512 } 513 } 514 515 NV_INFO(dev, "%d MiB GART (aperture)\n", 516 (int)(dev_priv->gart_info.aper_size >> 20)); 517 dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size; 518 519 ret = ttm_bo_init_mm(bdev, TTM_PL_TT, 520 dev_priv->gart_info.aper_size >> PAGE_SHIFT); 521 if (ret) { 522 NV_ERROR(dev, "Failed TT mm init: %d\n", ret); 523 return ret; 524 } 525 526 dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1), 527 pci_resource_len(dev->pdev, 1), 528 DRM_MTRR_WC); 529 530 return 0; 531} 532