/linux-master/arch/parisc/include/asm/ |
H A D | asmregs.h | 121 sar: .reg %cr11
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H A D | elf.h | 263 * cr11 (sar) 284 dst[44] = pt->sar; dst[45] = pt->iir; \
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H A D | kgdb.h | 33 unsigned long sar; member in struct:parisc_gdb_regs
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/linux-master/arch/parisc/include/uapi/asm/ |
H A D | ptrace.h | 35 unsigned long sar; /* CR11 */ member in struct:pt_regs 56 unsigned long sar; /* CR11 */ member in struct:user_regs_struct
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/linux-master/arch/parisc/kernel/ |
H A D | perf_asm.S | 154 shrpd ret0,%r0,%sar,%r1 178 shrpd ret0,%r0,%sar,%r1 274 shrpd ret0,%r0,%sar,%r1 286 shrpd ret0,%r0,%sar,%r1 322 shrpd ret0,%r0,%sar,%r1 358 shrpd ret0,%r0,%sar,%r1 370 shrpd ret0,%r0,%sar,%r1 466 shrpd ret0,%r0,%sar,%r1 478 shrpd ret0,%r0,%sar,%r1 514 shrpd ret0,%r0,%sar, [all...] |
H A D | signal32.c | 98 /* Load the upper half for sar */ 100 regs->sar = ((u64)compat_regt << 32) | (u64)compat_reg; 101 DBG(2,"restore_sigcontext32: upper_half & sar = %#lx\n", compat_regt); 102 DBG(2,"restore_sigcontext32: sar is %#lx\n", regs->sar); 238 compat_reg = (compat_uint_t)(regs->sar); 240 DBG(2,"setup_sigcontext32: sar is %#x\n", compat_reg); 242 compat_reg = (compat_uint_t)(regs->sar >> 32); 244 DBG(2,"setup_sigcontext32: upper half sar = %#x\n", compat_reg);
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H A D | asm-offsets.c | 130 DEFINE(TASK_PT_SAR, offsetof(struct task_struct, thread.regs.sar)); 215 DEFINE(PT_SAR, offsetof(struct pt_regs, sar));
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H A D | kgdb.c | 81 gr->sar = regs->sar; 112 regs->sar = gr->sar;
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H A D | ptrace.c | 454 case RI(sar): return regs->sar; 500 case RI(sar): regs->sar = val; 720 REG_OFFSET_NAME(sar),
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H A D | signal.c | 69 err |= __get_user(regs->sar, &sc->sc_sar); 206 err |= __put_user(regs->sar, &sc->sc_sar);
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H A D | toc.c | 35 regs->sar = (unsigned long)toc->cr[11]; 58 regs->sar = toc->cr[11];
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H A D | traps.c | 372 regs->sar = pim_wide->cr[11]; 396 regs->sar = pim_narrow->cr[11];
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/linux-master/arch/sh/drivers/dma/ |
H A D | dma-g2.c | 97 if (chan->sar & 31) { 98 printk("g2dma: unaligned source 0x%lx\n", chan->sar); 117 flush_icache_range((unsigned long)chan->sar, chan->count); 122 g2_dma->channel[chan_nr].root_addr = chan->sar & 0x1fffffe0; 136 pr_debug("count, sar, dar, mode, ctrl, chan, xfer: %ld, 0x%08lx, "
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H A D | dma-api.c | 288 channel->sar = from;
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/linux-master/drivers/clk/mvebu/ |
H A D | armada-370.c | 45 static u32 __init a370_get_tclk_freq(void __iomem *sar) argument 49 tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) & 64 static u32 __init a370_get_cpu_freq(void __iomem *sar) argument 69 cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) & 114 void __iomem *sar, int id, int *mult, int *div) 116 u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) & 135 static bool a370_is_sscg_enabled(void __iomem *sar) argument 137 return !(readl(sar) & SARL_A370_SSCG_ENABLE); 113 a370_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) argument
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H A D | armada-375.c | 50 static u32 __init armada_375_get_tclk_freq(void __iomem *sar) argument 54 tclk_freq_select = ((readl(sar) >> SAR1_A375_TCLK_FREQ_OPT) & 71 static u32 __init armada_375_get_cpu_freq(void __iomem *sar) argument 75 cpu_freq_select = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) & 115 void __iomem *sar, int id, int *mult, int *div) 117 u32 opt = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) & 114 armada_375_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) argument
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H A D | armada-38x.c | 37 static u32 __init armada_38x_get_tclk_freq(void __iomem *sar) argument 41 tclk_freq_select = ((readl(sar) >> SAR_A380_TCLK_FREQ_OPT) & 54 static u32 __init armada_38x_get_cpu_freq(void __iomem *sar) argument 58 cpu_freq_select = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) & 99 void __iomem *sar, int id, int *mult, int *div) 101 u32 opt = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) & 98 armada_38x_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) argument
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H A D | armada-39x.c | 45 static u32 __init armada_39x_get_tclk_freq(void __iomem *sar) argument 49 tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) & 68 static u32 __init armada_39x_get_cpu_freq(void __iomem *sar) argument 72 cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) & 92 void __iomem *sar, int id, int *mult, int *div) 110 static u32 __init armada_39x_refclk_ratio(void __iomem *sar) argument 112 if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ) 91 armada_39x_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) argument
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H A D | common.h | 28 u32 (*get_tclk_freq)(void __iomem *sar); 29 u32 (*get_cpu_freq)(void __iomem *sar); 30 void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div); 31 u32 (*get_refclk_freq)(void __iomem *sar); 32 bool (*is_sscg_enabled)(void __iomem *sar);
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H A D | dove.c | 87 static u32 __init dove_get_tclk_freq(void __iomem *sar) argument 89 u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) & 106 static u32 __init dove_get_cpu_freq(void __iomem *sar) argument 108 u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) & 126 void __iomem *sar, int id, int *mult, int *div) 131 u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) & 139 u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) & 125 dove_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) argument
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H A D | mv98dx3236.c | 44 static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar) argument 68 static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar) argument 73 cpu_freq_select = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) & 118 void __iomem *sar, int id, int *mult, int *div) 120 u32 opt = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) & 117 mv98dx3236_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) argument
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H A D | orion.c | 28 static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar) argument 30 u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) & 45 static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar) argument 47 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & 59 static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id, argument 62 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & 98 static u32 __init mv88f5182_get_tclk_freq(void __iomem *sar) argument 100 u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) & 113 static u32 __init mv88f5182_get_cpu_freq(void __iomem *sar) argument 115 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FRE 127 mv88f5182_get_clk_ratio(void __iomem *sar, int id, int *mult, int *div) argument 163 mv88f5281_get_tclk_freq(void __iomem *sar) argument 172 mv88f5281_get_cpu_freq(void __iomem *sar) argument 184 mv88f5281_get_clk_ratio(void __iomem *sar, int id, int *mult, int *div) argument 223 mv88f6183_get_tclk_freq(void __iomem *sar) argument 238 mv88f6183_get_cpu_freq(void __iomem *sar) argument 250 mv88f6183_get_clk_ratio(void __iomem *sar, int id, int *mult, int *div) argument [all...] |
/linux-master/drivers/dma/ |
H A D | idma64.h | 97 u64 sar; member in struct:idma64_lli
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/linux-master/sound/soc/fsl/ |
H A D | fsl_dma.h | 17 __be32 sar; /* Source address register */ member in struct:ccsr_dma::ccsr_dma_channel
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/linux-master/arch/parisc/lib/ |
H A D | lusercopy.S | 295 shrpw a2, a3, %sar, t0 301 shrpw a3, a0, %sar, t0 307 shrpw a0, a1, %sar, t0 313 shrpw a1, a2, %sar, t0 320 shrpw a2, a3, %sar, t0
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