Searched refs:queue_id (Results 1 - 25 of 205) sorted by path

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/linux-master/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_hw.c2284 u32 queue_id, read_addr, read_value, read_stride, select_addr, read_cnt; local
2290 for (loop_cnt = 0, queue_id = 0; loop_cnt < queueEntry->op_count;
2292 NX_WR_DUMP_REG(select_addr, adapter->ahw.pci_base0, queue_id);
2300 queue_id += queueEntry->queue_id_stride;
/linux-master/drivers/net/wireless/st/cw1200/
H A Ddebug.c73 seq_printf(seq, "Queue %d:\n", q->queue_id);
H A Dqueue.h40 u8 queue_id; member in struct:cw1200_queue
70 u8 queue_id,
/linux-master/drivers/net/wireless/ti/wlcore/
H A Dacx.c860 u8 queue_id, u8 channel_type,
877 acx->queue_id = queue_id;
859 wl1271_acx_tid_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif, u8 queue_id, u8 channel_type, u8 tsid, u8 ps_scheme, u8 ack_policy, u32 apsd_conf0, u32 apsd_conf1) argument
H A Dinit.c622 conf_tid->queue_id,
/linux-master/arch/mips/cavium-octeon/executive/
H A Dcvmx-cmd-queue.c101 * @queue_id: Hardware command queue to initialize.
108 cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, argument
117 qstate = __cvmx_cmd_queue_get_state(queue_id);
188 ticket[__cvmx_cmd_queue_get_index(queue_id)] = 0;
199 * @queue_id: Queue to shutdown
203 cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id) argument
205 __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
212 if (cvmx_cmd_queue_length(queue_id) > 0) {
218 __cvmx_cmd_queue_lock(queue_id, qptr);
234 * @queue_id
238 cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id) argument
296 cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id) argument
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/linux-master/arch/mips/include/asm/octeon/
H A Dcvmx-cmd-queue.h163 * @queue_id: Hardware command queue to initialize.
170 cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
179 * @queue_id: Queue to shutdown
183 cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id);
189 * @queue_id: Hardware command queue to query
193 int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id);
201 * @queue_id: Command queue to query
205 void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id);
210 * @queue_id: Queue ID to get an index for
214 static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id) argument
236 __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id, __cvmx_cmd_queue_state_t *qptr) argument
303 __cvmx_cmd_queue_get_state(cvmx_cmd_queue_id_t queue_id) argument
326 cvmx_cmd_queue_write(cvmx_cmd_queue_id_t queue_id, int use_locking, int cmd_count, uint64_t *cmds) argument
424 cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t queue_id, int use_locking, uint64_t cmd1, uint64_t cmd2) argument
524 cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t queue_id, int use_locking, uint64_t cmd1, uint64_t cmd2, uint64_t cmd3) argument
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/linux-master/drivers/accel/habanalabs/common/
H A Dhabanalabs.h1644 void* (*get_int_queue_base)(struct hl_device *hdev, u32 queue_id,
/linux-master/drivers/accel/habanalabs/gaudi/
H A Dgaudi.c498 get_collective_mode(struct hl_device *hdev, u32 queue_id) argument
500 if (gaudi_queue_type[queue_id] == QUEUE_TYPE_EXT)
503 if (queue_id >= GAUDI_QUEUE_ID_DMA_5_0 &&
504 queue_id <= GAUDI_QUEUE_ID_DMA_5_3)
507 if (queue_id >= GAUDI_QUEUE_ID_TPC_7_0 &&
508 queue_id <= GAUDI_QUEUE_ID_TPC_7_3)
511 if (queue_id >= GAUDI_QUEUE_ID_NIC_0_0 &&
512 queue_id <= GAUDI_QUEUE_ID_NIC_9_3)
1097 u32 i, sob_id, sob_group_id, queue_id; local
1104 queue_id
1212 u32 master_sob_base, master_monitor, queue_id, cb_size = 0; local
1265 u32 queue_id, cb_size = 0; local
1316 u32 stream, queue_id, sob_group_offset; local
1428 gaudi_collective_wait_create_job(struct hl_device *hdev, struct hl_ctx *ctx, struct hl_cs *cs, enum hl_collective_mode mode, u32 queue_id, u32 wait_queue_id, u32 encaps_signal_offset) argument
1531 u32 queue_id, collective_queue, num_jobs; local
4664 gaudi_get_int_queue_base(struct hl_device *hdev, u32 queue_id, dma_addr_t *dma_handle, u16 *queue_len) argument
8568 gaudi_get_fence_addr(struct hl_device *hdev, u32 queue_id, u64 *addr) argument
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H A DgaudiP.h262 * @queue_id: id of the queue that waits on this sob group
268 u32 queue_id; member in struct:gaudi_hw_sob_group
/linux-master/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2.c2313 static bool gaudi2_is_edma_queue_id(u32 queue_id) argument
2316 switch (queue_id) {
3868 * @queue_id: queue to clear fence counters to
3873 static void gaudi2_clear_qm_fence_counters_common(struct hl_device *hdev, u32 queue_id, argument
3879 reg_base = gaudi2_qm_blocks_bases[queue_id];
3894 static void gaudi2_qman_manual_flush_common(struct hl_device *hdev, u32 queue_id) argument
3896 u32 reg_base = gaudi2_qm_blocks_bases[queue_id];
3898 gaudi2_clear_qm_fence_counters_common(hdev, queue_id, true);
3990 u32 reg_base, queue_id; local
3996 queue_id
4186 u32 reg_base, queue_id; local
4655 u32 queue_id; local
5572 u32 i, reg_base, queue_id; local
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/linux-master/drivers/accel/habanalabs/goya/
H A Dgoya.c3015 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id, argument
3025 switch (queue_id) {
3063 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
H A DgoyaP.h237 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
/linux-master/drivers/block/
H A Dublk_drv.c2330 if (header->queue_id != (u16)-1) {
2331 pr_warn("%s: queue_id is wrong %x\n",
2332 __func__, header->queue_id);
2516 __func__, cmd->cmd_op, header->dev_id, header->queue_id,
2936 __func__, ret, cmd->cmd_op, header->dev_id, header->queue_id);
/linux-master/drivers/crypto/hisilicon/sec/
H A Dsec_drv.c234 2 + queue->queue_id);
237 queue->queue_id);
655 if (queue->queue_id >= SEC_Q_NUM) {
656 dev_err(info->dev, "No queue %u\n", queue->queue_id);
661 dev_err(info->dev, "Queue %u is idle\n", queue->queue_id);
1002 struct sec_queue *queue, int queue_id)
1005 queue->queue_id = queue_id;
1007 "%s_%d", dev_name(info->dev), queue->queue_id);
1109 queue->queue_id *
1001 sec_queue_base_init(struct sec_dev_info *info, struct sec_queue *queue, int queue_id) argument
1142 sec_queue_config(struct sec_dev_info *info, struct sec_queue *queue, int queue_id) argument
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H A Dsec_drv.h322 * @queue_id: Index of the queue used for naming and resource selection.
343 u32 queue_id; member in struct:sec_queue
/linux-master/drivers/crypto/hisilicon/sec2/
H A Dsec_crypto.c1753 int queue_id; local
1756 queue_id = sec_alloc_queue_id(ctx, req);
1757 qp_ctx = &ctx->qp_ctx[queue_id];
/linux-master/drivers/crypto/virtio/
H A Dvirtio_crypto_akcipher_algs.c189 ctrl->header.queue_id = 0;
417 header.queue_id = 0;
H A Dvirtio_crypto_skcipher_algs.c147 ctrl->header.queue_id = 0;
215 ctrl->header.queue_id = 0;
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_arcturus.c70 unsigned int queue_id)
116 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
119 queue_id, sdma_rlc_reg_offset);
194 uint32_t engine_id, uint32_t queue_id,
198 engine_id, queue_id);
68 get_sdma_rlc_reg_offset(struct amdgpu_device *adev, unsigned int engine_id, unsigned int queue_id) argument
193 kgd_arcturus_hqd_sdma_dump(struct amdgpu_device *adev, uint32_t engine_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs) argument
H A Damdgpu_amdkfd_arcturus.h26 uint32_t engine_id, uint32_t queue_id,
H A Damdgpu_amdkfd_gc_9_4_3.c45 unsigned int queue_id)
52 queue_id * (regSDMA_RLC1_RB_CNTL - regSDMA_RLC0_RB_CNTL);
55 queue_id, retval);
129 uint32_t engine_id, uint32_t queue_id,
133 engine_id, queue_id);
285 uint32_t pipe_id, uint32_t queue_id,
295 kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);
347 (uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id));
43 get_sdma_rlc_reg_offset(struct amdgpu_device *adev, unsigned int engine_id, unsigned int queue_id) argument
128 kgd_gfx_v9_4_3_hqd_sdma_dump(struct amdgpu_device *adev, uint32_t engine_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs) argument
284 kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst) argument
H A Damdgpu_amdkfd_gfx_v10.c58 uint32_t queue_id)
63 lock_srbm(adev, mec, pipe, queue_id, 0);
67 uint32_t pipe_id, uint32_t queue_id)
70 queue_id;
162 unsigned int queue_id)
178 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
181 queue_id, retval);
209 uint32_t pipe_id, uint32_t queue_id,
219 pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id);
220 acquire_queue(adev, pipe_id, queue_id);
57 acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t queue_id) argument
66 get_queue_mask(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t queue_id) argument
160 get_sdma_rlc_reg_offset(struct amdgpu_device *adev, unsigned int engine_id, unsigned int queue_id) argument
208 kgd_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst) argument
290 kgd_hiq_mqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t doorbell_off, uint32_t inst) argument
342 kgd_hqd_dump(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst) argument
442 kgd_hqd_sdma_dump(struct amdgpu_device *adev, uint32_t engine_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs) argument
473 kgd_hqd_is_occupied(struct amdgpu_device *adev, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id, uint32_t inst) argument
513 kgd_hqd_destroy(struct amdgpu_device *adev, void *mqd, enum kfd_preempt_type reset_type, unsigned int utimeout, uint32_t pipe_id, uint32_t queue_id, uint32_t inst) argument
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H A Damdgpu_amdkfd_gfx_v10_3.c58 uint32_t queue_id)
63 lock_srbm(adev, mec, pipe, queue_id, 0);
67 uint32_t pipe_id, uint32_t queue_id)
70 queue_id;
131 unsigned int queue_id)
161 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
164 queue_id, sdma_rlc_reg_offset);
180 uint32_t pipe_id, uint32_t queue_id,
190 pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id);
191 acquire_queue(adev, pipe_id, queue_id);
57 acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t queue_id) argument
66 get_queue_mask(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t queue_id) argument
129 get_sdma_rlc_reg_offset(struct amdgpu_device *adev, unsigned int engine_id, unsigned int queue_id) argument
179 hqd_load_v10_3(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst) argument
276 hiq_mqd_load_v10_3(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t doorbell_off, uint32_t inst) argument
328 hqd_dump_v10_3(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst) argument
428 hqd_sdma_dump_v10_3(struct amdgpu_device *adev, uint32_t engine_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs) argument
459 hqd_is_occupied_v10_3(struct amdgpu_device *adev, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id, uint32_t inst) argument
500 hqd_destroy_v10_3(struct amdgpu_device *adev, void *mqd, enum kfd_preempt_type reset_type, unsigned int utimeout, uint32_t pipe_id, uint32_t queue_id, uint32_t inst) argument
[all...]
H A Damdgpu_amdkfd_gfx_v11.c56 uint32_t queue_id)
61 lock_srbm(adev, mec, pipe, queue_id, 0);
65 uint32_t pipe_id, uint32_t queue_id)
68 queue_id;
127 unsigned int queue_id)
146 + queue_id * (regSDMA0_QUEUE1_RB_CNTL - regSDMA0_QUEUE0_RB_CNTL);
149 queue_id, sdma_rlc_reg_offset);
165 uint32_t queue_id, uint32_t __user *wptr,
175 pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id);
176 acquire_queue(adev, pipe_id, queue_id);
55 acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t queue_id) argument
64 get_queue_mask(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t queue_id) argument
125 get_sdma_rlc_reg_offset(struct amdgpu_device *adev, unsigned int engine_id, unsigned int queue_id) argument
164 hqd_load_v11(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst) argument
261 hiq_mqd_load_v11(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t doorbell_off, uint32_t inst) argument
313 hqd_dump_v11(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst) argument
413 hqd_sdma_dump_v11(struct amdgpu_device *adev, uint32_t engine_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs) argument
449 hqd_is_occupied_v11(struct amdgpu_device *adev, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id, uint32_t inst) argument
488 hqd_destroy_v11(struct amdgpu_device *adev, void *mqd, enum kfd_preempt_type reset_type, unsigned int utimeout, uint32_t pipe_id, uint32_t queue_id, uint32_t inst) argument
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