/linux-master/arch/arm/include/asm/ |
H A D | barrier.h | 82 static inline unsigned long array_index_mask_nospec(unsigned long idx, argument 92 : "r" (idx), "Ir" (sz)
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/linux-master/arch/arm/mach-omap2/ |
H A D | prminst44xx.c | 58 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) argument 63 return readl_relaxed(_prm_bases[part].va + inst + idx); 67 void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) argument 72 writel_relaxed(val, _prm_bases[part].va + inst + idx); 77 u16 idx) 81 v = omap4_prminst_read_inst_reg(part, inst, idx); 84 omap4_prminst_write_inst_reg(v, part, inst, idx); 76 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, u16 idx) argument
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H A D | prminst44xx.h | 20 extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx); 21 extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx); 23 s16 inst, u16 idx);
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/linux-master/arch/arm/mm/ |
H A D | cache-l2x0-pmu.c | 34 * We ensure that idx 0 -> Counter0, and idx1 -> Counter1. 64 static void l2x0_pmu_counter_config_write(int idx, u32 val) argument 66 writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_CFG - 4 * idx); 69 static u32 l2x0_pmu_counter_read(int idx) argument 71 return readl_relaxed(l2x0_base + L2X0_EVENT_CNT0_VAL - 4 * idx); 74 static void l2x0_pmu_counter_write(int idx, u32 val) argument 76 writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_VAL - 4 * idx); 124 new_count = l2x0_pmu_counter_read(hw->idx); 148 l2x0_pmu_counter_write(hw->idx, 0); 177 static void __l2x0_pmu_event_enable(int idx, u3 argument 203 __l2x0_pmu_event_disable(int idx) argument 232 int idx = l2x0_pmu_find_idx(); local [all...] |
/linux-master/arch/mips/include/asm/sibyte/ |
H A D | bcm1480_regs.h | 539 #define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) 540 #define A_BCM1480_HR_REGISTER(idx, reg) (A_BCM1480_HR_BASE(idx) + (reg)) 550 #define R_BCM1480_HR_RULE_OP(idx) (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) 551 #define R_BCM1480_HR_RULE_TYPE(idx) (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) 556 #define R_BCM1480_HR_HA_LEAF0(idx) (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACIN [all...] |
H A D | sb1250_regs.h | 576 #define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) 577 #define A_SMB_REGISTER(idx, reg) (A_SMB_BASE(idx)+(reg)) 810 #define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) 811 #define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg)) 824 #define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACIN [all...] |
/linux-master/arch/mips/include/asm/ |
H A D | tlb.h | 8 #define _UNIQUE_ENTRYHI(base, idx) \ 9 (((base) + ((idx) << (PAGE_SHIFT + 1))) | \ 11 #define UNIQUE_ENTRYHI(idx) _UNIQUE_ENTRYHI(CKSEG0, idx) 12 #define UNIQUE_GUEST_ENTRYHI(idx) _UNIQUE_ENTRYHI(CKSEG1, idx)
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/linux-master/arch/sh/kernel/cpu/sh2/ |
H A D | clock-sh7619.c | 34 int idx = (__raw_readw(FREQCR) & 0x0007); local 35 return clk->parent->rate / pfc_divisors[idx]; 62 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) argument 72 if (idx < ARRAY_SIZE(sh7619_clk_ops)) 73 *ops = sh7619_clk_ops[idx];
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/linux-master/arch/sh/kernel/cpu/sh2a/ |
H A D | clock-sh7201.c | 36 int idx = (__raw_readw(FREQCR) & 0x0007); local 37 return clk->parent->rate / pfc_divisors[idx]; 46 int idx = (__raw_readw(FREQCR) & 0x0007); local 47 return clk->parent->rate / pfc_divisors[idx]; 56 int idx = ((__raw_readw(FREQCR) >> 4) & 0x0007); local 57 return clk->parent->rate / ifc_divisors[idx]; 71 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) argument 80 if (idx < ARRAY_SIZE(sh7201_clk_ops)) 81 *ops = sh7201_clk_ops[idx];
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H A D | clock-sh7203.c | 38 int idx = (__raw_readw(FREQCR) & 0x0007); local 39 return clk->parent->rate / pfc_divisors[idx]; 48 int idx = (__raw_readw(FREQCR) & 0x0007); local 49 return clk->parent->rate / pfc_divisors[idx-2]; 67 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) argument 76 if (idx < ARRAY_SIZE(sh7203_clk_ops)) 77 *ops = sh7203_clk_ops[idx];
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H A D | clock-sh7206.c | 35 int idx = (__raw_readw(FREQCR) & 0x0007); local 36 return clk->parent->rate / pfc_divisors[idx]; 54 int idx = (__raw_readw(FREQCR) & 0x0007); local 55 return clk->parent->rate / ifc_divisors[idx]; 69 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) argument 78 if (idx < ARRAY_SIZE(sh7206_clk_ops)) 79 *ops = sh7206_clk_ops[idx];
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/linux-master/arch/sh/kernel/cpu/sh3/ |
H A D | clock-sh3.c | 29 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); local 31 clk->rate *= pfc_divisors[idx]; 41 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); local 43 return clk->parent->rate / pfc_divisors[idx]; 53 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4); local 55 return clk->parent->rate / stc_multipliers[idx]; 65 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); local 67 return clk->parent->rate / ifc_divisors[idx]; 81 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) argument 83 if (idx < ARRAY_SIZ [all...] |
H A D | clock-sh7705.c | 41 int idx = __raw_readw(FRQCR) & 0x0003; local 42 return clk->parent->rate / pfc_divisors[idx]; 51 int idx = (__raw_readw(FRQCR) & 0x0300) >> 8; local 52 return clk->parent->rate / stc_multipliers[idx]; 61 int idx = (__raw_readw(FRQCR) & 0x0030) >> 4; local 62 return clk->parent->rate / ifc_divisors[idx]; 76 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) argument 78 if (idx < ARRAY_SIZE(sh7705_clk_ops)) 79 *ops = sh7705_clk_ops[idx];
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H A D | clock-sh7706.c | 25 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); local 27 clk->rate *= pfc_divisors[idx]; 37 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); local 39 return clk->parent->rate / pfc_divisors[idx]; 49 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4); local 51 return clk->parent->rate / stc_multipliers[idx]; 61 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); local 63 return clk->parent->rate / ifc_divisors[idx]; 77 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) argument 79 if (idx < ARRAY_SIZ [all...] |
H A D | clock-sh7709.c | 25 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); local 27 clk->rate *= pfc_divisors[idx]; 37 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); local 39 return clk->parent->rate / pfc_divisors[idx]; 49 int idx = (frqcr & 0x0080) ? local 52 return clk->parent->rate * stc_multipliers[idx]; 62 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); local 64 return clk->parent->rate / ifc_divisors[idx]; 78 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) argument 80 if (idx < ARRAY_SIZ [all...] |
H A D | clock-sh7710.c | 35 int idx = (__raw_readw(FRQCR) & 0x0007); local 36 return clk->parent->rate / md_table[idx]; 45 int idx = (__raw_readw(FRQCR) & 0x0700) >> 8; local 46 return clk->parent->rate / md_table[idx]; 55 int idx = (__raw_readw(FRQCR) & 0x0070) >> 4; local 56 return clk->parent->rate / md_table[idx]; 70 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) argument 72 if (idx < ARRAY_SIZE(sh7710_clk_ops)) 73 *ops = sh7710_clk_ops[idx];
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H A D | clock-sh7712.c | 24 int idx = (frqcr & 0x0300) >> 8; local 26 clk->rate *= multipliers[idx]; 36 int idx = frqcr & 0x0007; local 38 return clk->parent->rate / divisors[idx]; 48 int idx = (frqcr & 0x0030) >> 4; local 50 return clk->parent->rate / divisors[idx]; 63 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) argument 65 if (idx < ARRAY_SIZE(sh7712_clk_ops)) 66 *ops = sh7712_clk_ops[idx];
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/linux-master/arch/sh/kernel/cpu/sh4/ |
H A D | clock-sh4.c | 37 int idx = (__raw_readw(FRQCR) & 0x0007); local 38 return clk->parent->rate / pfc_divisors[idx]; 47 int idx = (__raw_readw(FRQCR) >> 3) & 0x0007; local 48 return clk->parent->rate / bfc_divisors[idx]; 57 int idx = (__raw_readw(FRQCR) >> 6) & 0x0007; local 58 return clk->parent->rate / ifc_divisors[idx]; 72 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) argument 74 if (idx < ARRAY_SIZE(sh4_clk_ops)) 75 *ops = sh4_clk_ops[idx];
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H A D | perf_event.c | 202 static u64 sh7750_pmu_read(int idx) argument 204 return (u64)((u64)(__raw_readl(PMCTRH(idx)) & 0xffff) << 32) | 205 __raw_readl(PMCTRL(idx)); 208 static void sh7750_pmu_disable(struct hw_perf_event *hwc, int idx) argument 212 tmp = __raw_readw(PMCR(idx)); 214 __raw_writew(tmp, PMCR(idx)); 217 static void sh7750_pmu_enable(struct hw_perf_event *hwc, int idx) argument 219 __raw_writew(__raw_readw(PMCR(idx)) | PMCR_PMCLR, PMCR(idx)); 220 __raw_writew(hwc->config | PMCR_PMEN | PMCR_PMST, PMCR(idx)); [all...] |
/linux-master/arch/sh/kernel/cpu/sh4a/ |
H A D | clock-sh7763.c | 33 int idx = ((__raw_readl(FRQCR) >> 4) & 0x07); local 34 return clk->parent->rate / p0fc_divisors[idx]; 43 int idx = ((__raw_readl(FRQCR) >> 16) & 0x07); local 44 return clk->parent->rate / bfc_divisors[idx]; 62 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) argument 64 if (idx < ARRAY_SIZE(sh7763_clk_ops)) 65 *ops = sh7763_clk_ops[idx]; 70 int idx = ((__raw_readl(FRQCR) >> 20) & 0x07); local 71 return clk->parent->rate / cfc_divisors[idx];
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H A D | clock-sh7770.c | 30 int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f); local 31 return clk->parent->rate / pfc_divisors[idx]; 40 int idx = (__raw_readl(FRQCR) & 0x000f); local 41 return clk->parent->rate / bfc_divisors[idx]; 50 int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f); local 51 return clk->parent->rate / ifc_divisors[idx]; 65 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) argument 67 if (idx < ARRAY_SIZE(sh7770_clk_ops)) 68 *ops = sh7770_clk_ops[idx];
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H A D | clock-sh7780.c | 33 int idx = (__raw_readl(FRQCR) & 0x0003); local 34 return clk->parent->rate / pfc_divisors[idx]; 43 int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007); local 44 return clk->parent->rate / bfc_divisors[idx]; 53 int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001); local 54 return clk->parent->rate / ifc_divisors[idx]; 68 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) argument 70 if (idx < ARRAY_SIZE(sh7780_clk_ops)) 71 *ops = sh7780_clk_ops[idx]; 76 int idx local [all...] |
H A D | perf_event.c | 14 #define PPC_CCBR(idx) (0xff200800 + (sizeof(u32) * idx)) 15 #define PPC_PMCTR(idx) (0xfc100000 + (sizeof(u32) * idx)) 227 static u64 sh4a_pmu_read(int idx) argument 229 return __raw_readl(PPC_PMCTR(idx)); 232 static void sh4a_pmu_disable(struct hw_perf_event *hwc, int idx) argument 236 tmp = __raw_readl(PPC_CCBR(idx)); 238 __raw_writel(tmp, PPC_CCBR(idx)); 241 static void sh4a_pmu_enable(struct hw_perf_event *hwc, int idx) argument [all...] |
H A D | ubc.c | 15 #define UBC_CBR(idx) (0xff200000 + (0x20 * idx)) 16 #define UBC_CRR(idx) (0xff200004 + (0x20 * idx)) 17 #define UBC_CAR(idx) (0xff200008 + (0x20 * idx)) 18 #define UBC_CAMR(idx) (0xff20000c + (0x20 * idx)) 32 static void sh4a_ubc_enable(struct arch_hw_breakpoint *info, int idx) argument 34 __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx)); 38 sh4a_ubc_disable(struct arch_hw_breakpoint *info, int idx) argument [all...] |
/linux-master/arch/sparc/kernel/ |
H A D | sun4d_irq.c | 110 unsigned int idx, mask; local 124 for (idx = 0; mask != 0; idx++, slot <<= 1) { 132 pil = sun4d_encode_irq(sbino, sbusl, idx);
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