Searched refs:_parent (Results 1 - 25 of 204) sorted by path

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/linux-master/arch/sh/kernel/cpu/sh4a/
H A D	clock-sh7343.c	125 #define MSTP(_parent, _reg, _bit, _flags) \ 126 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
H A D	clock-sh7366.c	128 #define MSTP(_parent, _reg, _bit, _flags) \ 129 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
/linux-master/drivers/clk/actions/
H A D	owl-composite.h	37 #define OWL_COMP_DIV(_struct, _name, _parent, \ 46 _parent, \ 52 #define OWL_COMP_DIV_FIXED(_struct, _name, _parent, \ 60 _parent, \ 66 #define OWL_COMP_FACTOR(_struct, _name, _parent, \ 75 _parent, \ 81 #define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent, \ 91 _parent, \ 97 #define OWL_COMP_PASS(_struct, _name, _parent, \ 105 _parent, \ [all...]
H A D	owl-divider.h	38 #define OWL_DIVIDER(_struct, _name, _parent, _reg, \ 46 _parent, \
H A D	owl-factor.h	44 #define OWL_FACTOR(_struct, _name, _parent, _reg, \ 52 _parent, \
H A D	owl-fixed-factor.h	16 #define OWL_FIX_FACT(_struct, _name, _parent, _mul, _div, _flags) \ 21 _parent, \
H A D	owl-gate.h	34 #define OWL_GATE(_struct, _name, _parent, _reg, \ 41 _parent, \
H A D	owl-pll.h	55 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ 64 _parent, \
/linux-master/drivers/clk/sunxi-ng/
H A D	ccu_mult.h	45 #define SUNXI_CCU_N_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ 55 _parent, \
H A D	ccu_nk.h	33 #define SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(_struct, _name, _parent, _reg, \ 48 _parent, \
H A D	ccu_nkm.h	56 #define SUNXI_CCU_NKM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ 70 _parent, \
H A D	ccu_nkmp.h	35 #define SUNXI_CCU_NKMP_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ 51 _parent, \
H A D	ccu_phase.h	20 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ 27 _parent, \
/linux-master/include/linux/
H A D	sh_clk.h	117 #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \ 119 .parent = _parent, \ 151 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ 153 .parent = _parent, \ 188 #define SH_CLK_DIV6(_parent, _reg, _flags) \ 190 .parent = _parent, \ 205 #define SH_CLK_FSIDIV(_reg, _parent) \ 208 .parent = _parent, \
/linux-master/drivers/clk/
H A D	clk-bm1880.c	143 #define GATE_DIV(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ 147 .parent = _parent, \ 174 #define CLK_PLL(_id, _name, _parent, _reg, _flags) { \ 178 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, \ 183 #define CLK_DIV(_id, _name, _parent, _reg, _shift, _width, _initval, \ 192 .hw.init = CLK_HW_INIT_HW(_name, _parent, \
H A D	clk-stm32h7.c	598 #define OSC_CLKF(_name, _parent, _gate_offset, _bit_idx, _bit_rdy, _flags)\ 601 .parent = _parent,\ 608 #define OSC_CLK(_name, _parent, _gate_offset, _bit_idx, _bit_rdy)\ 609 OSC_CLKF(_name, _parent, _gate_offset, _bit_idx, _bit_rdy, 0) 937 #define M_ODF_F(_name, _parent, _gate_offset, _bit_idx, _rate_offset,\ 944 .parent_name = &(const char *) {_parent},\ 949 #define M_ODF(_name, _parent, _gate_offset, _bit_idx, _rate_offset,\ 951 M_ODF_F(_name, _parent, _gate_offset, _bit_idx, _rate_offset,\ 985 #define PER_CLKF(_gate_offset, _bit_idx, _name, _parent, _flags)\ 990 .parent = _parent,\ [all...]
/linux-master/drivers/clk/mediatek/
H A D	clk-gate.h	39 #define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \ 43 .parent_name = _parent, \ 50 #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \ 51 GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
H A D	clk-mt2701-aud.c	18 #define GATE_AUDIO0(_id, _name, _parent, _shift) \ 19 GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 21 #define GATE_AUDIO1(_id, _name, _parent, _shift) \ 22 GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 24 #define GATE_AUDIO2(_id, _name, _parent, _shift) \ 25 GATE_MTK(_id, _name, _parent, &audio2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 27 #define GATE_AUDIO3(_id, _name, _parent, _shift) \ 28 GATE_MTK(_id, _name, _parent, &audio3_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
H A D	clk-mt2701-bdp.c	27 #define GATE_BDP0(_id, _name, _parent, _shift) \ 28 GATE_MTK(_id, _name, _parent, &bdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) 30 #define GATE_BDP1(_id, _name, _parent, _shift) \ 31 GATE_MTK(_id, _name, _parent, &bdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A D	clk-mt2701-eth.c	19 #define GATE_ETH(_id, _name, _parent, _shift) \ 20 GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
H A D	clk-mt2701-g3d.c	17 #define GATE_G3D(_id, _name, _parent, _shift) \ 18 GATE_MTK(_id, _name, _parent, &g3d_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
H A D	clk-mt2701-hif.c	19 #define GATE_HIF(_id, _name, _parent, _shift) \ 20 GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
H A D	clk-mt2701-img.c	21 #define GATE_IMG(_id, _name, _parent, _shift) \ 22 GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
H A D	clk-mt2701-mm.c	27 #define GATE_DISP0(_id, _name, _parent, _shift) \ 28 GATE_MTK(_id, _name, _parent, &disp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 30 #define GATE_DISP1(_id, _name, _parent, _shift) \ 31 GATE_MTK(_id, _name, _parent, &disp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
H A D	clk-mt2701-vdec.c	27 #define GATE_VDEC0(_id, _name, _parent, _shift) \ 28 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) 30 #define GATE_VDEC1(_id, _name, _parent, _shift) \ 31 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)

Completed in 224 milliseconds

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Indexes created Thu May 16 13:05:45 MDT 2024