/linux-master/arch/arm/include/asm/ |
H A D | cti.h | 92 __raw_writel(val, base + CTIINEN + trig_in * 4); 96 __raw_writel(val, base + CTIOUTEN + trig_out * 4); 107 __raw_writel(0x1, cti->base + CTICONTROL); 118 __raw_writel(0, cti->base + CTICONTROL); 134 __raw_writel(val, base + CTIINTACK); 146 __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS); 158 __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS);
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/linux-master/arch/arm/include/asm/hardware/ |
H A D | iomd.h | 23 #define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off))
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/linux-master/arch/arm/kernel/ |
H A D | v7m.c | 13 __raw_writel(V7M_SCB_AIRCR_VECTKEY | V7M_SCB_AIRCR_SYSRESETREQ,
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/linux-master/arch/arm/mach-rpc/include/mach/ |
H A D | hardware.h | 57 #define vidc_writel(val) __raw_writel(val, VIDC_BASE)
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/linux-master/arch/arm/mach-sti/ |
H A D | platsmp.c | 40 __raw_writel(entry_pa, cpu_strt_ptr);
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/linux-master/arch/mips/alchemy/common/ |
H A D | irq.c | 293 __raw_writel(1 << bit, base + IC_MASKSET); 294 __raw_writel(1 << bit, base + IC_WAKESET); 303 __raw_writel(1 << bit, base + IC_MASKSET); 304 __raw_writel(1 << bit, base + IC_WAKESET); 313 __raw_writel(1 << bit, base + IC_MASKCLR); 314 __raw_writel(1 << bit, base + IC_WAKECLR); 323 __raw_writel(1 << bit, base + IC_MASKCLR); 324 __raw_writel(1 << bit, base + IC_WAKECLR); 337 __raw_writel(1 << bit, base + IC_FALLINGCLR); 338 __raw_writel( [all...] |
H A D | usb.c | 112 __raw_writel(r, base + USB_DWC_CTRL2); 118 __raw_writel(r, base + USB_DWC_CTRL2); 128 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ 134 __raw_writel(r, base + USB_DWC_CTRL3); 141 __raw_writel(r, base + USB_INT_ENABLE); 145 __raw_writel(0, base + USB_DWC_CTRL7); 150 __raw_writel(r, base + USB_INT_ENABLE); 156 __raw_writel(r, base + USB_DWC_CTRL3); 170 __raw_writel(r, base + USB_DWC_CTRL3); 175 __raw_writel( [all...] |
H A D | vss.c | 27 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ 30 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ 34 __raw_writel(0x01, base + VSS_FTR); 36 __raw_writel(0x03, base + VSS_FTR); 38 __raw_writel(0x07, base + VSS_FTR); 40 __raw_writel(0x0f, base + VSS_FTR); 43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ 46 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ 49 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ 58 __raw_writel( [all...] |
/linux-master/arch/mips/ath25/ |
H A D | early_printk.c | 21 __raw_writel(ch, base + 4 * reg);
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/linux-master/arch/mips/include/asm/mach-ath79/ |
H A D | ath79.h | 156 __raw_writel(val, ath79_pll_base + reg); 166 __raw_writel(val, ath79_reset_base + reg);
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/linux-master/arch/mips/include/asm/mach-lantiq/ |
H A D | lantiq.h | 15 #define ltq_w32(val, reg) __raw_writel(val, reg)
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/linux-master/arch/mips/include/asm/mach-ralink/ |
H A D | ralink_regs.h | 37 __raw_writel(val, rt_sysc_membase + reg); 49 __raw_writel(val | set, rt_sysc_membase + reg); 54 __raw_writel(val, rt_memc_membase + reg);
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/linux-master/arch/mips/include/asm/mach-rc32434/ |
H A D | dma_v.h | 30 __raw_writel(0, &ch->dmac); 33 __raw_writel(0, &ch->dmas); 44 __raw_writel(0, &ch->dmandptr); 45 __raw_writel(dma_addr, &ch->dmadptr); 50 __raw_writel(dma_addr, &ch->dmandptr);
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/linux-master/arch/mips/include/asm/ |
H A D | mips-gic.h | 68 __raw_writel(val, addr_gic_##name(intr)); \ 121 __raw_writel(BIT(intr % 32), addr); \ 145 __raw_writel(_val, addr); \
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/linux-master/arch/mips/kernel/ |
H A D | gpio_txx9.c | 32 __raw_writel(val, &txx9_pioptr->dout); 49 __raw_writel(__raw_readl(&txx9_pioptr->dir) & ~(1 << offset), 62 __raw_writel(__raw_readl(&txx9_pioptr->dir) | (1 << offset),
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/linux-master/arch/mips/pic32/common/ |
H A D | reset.c | 32 __raw_writel(1, reg);
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/linux-master/arch/mips/ralink/ |
H A D | early_printk.c | 37 __raw_writel(val, uart_membase + reg);
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/linux-master/arch/mips/sgi-ip22/ |
H A D | ip22-nvram.c | 36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \ 37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \ 38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \ 40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \ 41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); }) 45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \ 46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \ 47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \ 48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); }) 64 __raw_writel(__raw_read [all...] |
/linux-master/arch/parisc/lib/ |
H A D | io.c | 29 __raw_writel(*(u32 *)src, dst); 114 __raw_writel(val32, addr);
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/linux-master/arch/sh/boards/mach-dreamcast/ |
H A D | rtc.c | 68 __raw_writel((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H); 69 __raw_writel((adj & 0xffff), AICA_RTC_SECS_L);
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/linux-master/arch/sh/boards/mach-rsk/ |
H A D | devices-rsk7203.c | 131 __raw_writel(0x36db0400, 0xfffc0008); /* CS1BCR */
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/linux-master/arch/sh/boards/mach-se/7780/ |
H A D | irq.c | 47 __raw_writel(0xAAAA0000, INTC_ICR1);
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/linux-master/arch/sh/boards/mach-sh7763rdp/ |
H A D | irq.c | 28 __raw_writel(1 << 25, INTC_INT2MSKCR); 31 __raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000, 35 __raw_writel(1 << 17, INTC_INT2MSKCR1); 38 __raw_writel(1 << 16, INTC_INT2MSKCR1); 41 __raw_writel(1 << 8, INTC_INT2MSKCR);
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/linux-master/arch/sh/drivers/dma/ |
H A D | dmabrg.c | 90 __raw_writel(dcr & ~0x00ff0003, DMABRGCR); /* ack all */ 114 __raw_writel(dcr, DMABRGCR); 122 __raw_writel(dcr, DMABRGCR); 168 __raw_writel(0, DMABRGCR); 169 __raw_writel(0, DMACHCR0); 170 __raw_writel(0x94000000, DMARSRA); /* enable DMABRG in DMAC 0 */ 174 __raw_writel(or | DMAOR_BRG | DMAOR_DMEN, DMAOR);
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/linux-master/arch/sh/drivers/pci/ |
H A D | pci-sh4.h | 173 __raw_writel(val, chan->reg_base + reg);
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