Searched refs:VAL (Results 1 - 25 of 56) sorted by path

123

/linux-master/arch/sparc/include/asm/
H A Dtsb.h113 #define TSB_STORE(ADDR, VAL) \
114 661: stxa VAL, [ADDR] ASI_N; \
117 stxa VAL, [ADDR] ASI_PHYS_USE_EC; \
/linux-master/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_hdr.h950 #define NETXEN_DIMM_MEMTYPE(VAL) ((VAL >> 3) & 0xf)
951 #define NETXEN_DIMM_NUMROWS(VAL) ((VAL >> 7) & 0xf)
952 #define NETXEN_DIMM_NUMCOLS(VAL) ((VAL >> 11) & 0xf)
953 #define NETXEN_DIMM_NUMRANKS(VAL) ((VAL >> 15) & 0x3)
954 #define NETXEN_DIMM_DATAWIDTH(VAL) ((VAL >> 1
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/linux-master/drivers/scsi/
H A Daha152x.h289 #define SETPORT(PORT, VAL) outb( (VAL), (PORT) )
/linux-master/arch/arm/include/asm/
H A Dhw_breakpoint.h109 #define ARM_DBG_READ(N, M, OP2, VAL) do {\
110 asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
113 #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\
114 asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
/linux-master/arch/arm/kernel/
H A Dhw_breakpoint.c48 #define READ_WB_REG_CASE(OP2, M, VAL) \
50 ARM_DBG_READ(c0, c ## M, OP2, VAL); \
53 #define WRITE_WB_REG_CASE(OP2, M, VAL) \
55 ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \
58 #define GEN_READ_WB_REG_CASES(OP2, VAL) \
59 READ_WB_REG_CASE(OP2, 0, VAL); \
60 READ_WB_REG_CASE(OP2, 1, VAL); \
61 READ_WB_REG_CASE(OP2, 2, VAL); \
62 READ_WB_REG_CASE(OP2, 3, VAL); \
63 READ_WB_REG_CASE(OP2, 4, VAL); \
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/linux-master/arch/arm64/include/asm/
H A Dbarrier.h192 __unqual_scalar_typeof(*ptr) VAL; \
194 VAL = READ_ONCE(*__PTR); \
197 __cmpwait_relaxed(__PTR, VAL); \
199 (typeof(*ptr))VAL; \
205 __unqual_scalar_typeof(*ptr) VAL; \
207 VAL = smp_load_acquire(__PTR); \
210 __cmpwait_relaxed(__PTR, VAL); \
212 (typeof(*ptr))VAL; \
H A Dhw_breakpoint.h98 #define AARCH64_DBG_READ(N, REG, VAL) do {\
99 VAL = read_sysreg(dbg##REG##N##_el1);\
102 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\
103 write_sysreg(VAL, dbg##REG##N##_el1);\
H A Dmte.h87 smp_cond_load_acquire(&page->flags, VAL & (1UL << PG_mte_tagged));
/linux-master/arch/arm64/kernel/
H A Dhw_breakpoint.c60 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \
62 AARCH64_DBG_READ(N, REG, VAL); \
65 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \
67 AARCH64_DBG_WRITE(N, REG, VAL); \
70 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \
71 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
72 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
73 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
74 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
75 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
[all...]
/linux-master/arch/loongarch/include/asm/
H A Dhw_breakpoint.h57 #define LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL) \
60 VAL = csr_read64(LOONGARCH_CSR_##IB##N##REG); \
62 VAL = csr_read64(LOONGARCH_CSR_##DB##N##REG); \
65 #define LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL) \
68 csr_write64(VAL, LOONGARCH_CSR_##IB##N##REG); \
70 csr_write64(VAL, LOONGARCH_CSR_##DB##N##REG); \
/linux-master/arch/loongarch/kernel/
H A Dhw_breakpoint.c36 #define READ_WB_REG_CASE(OFF, N, REG, T, VAL) \
38 LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL); \
41 #define WRITE_WB_REG_CASE(OFF, N, REG, T, VAL) \
43 LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL); \
46 #define GEN_READ_WB_REG_CASES(OFF, REG, T, VAL) \
47 READ_WB_REG_CASE(OFF, 0, REG, T, VAL); \
48 READ_WB_REG_CASE(OFF, 1, REG, T, VAL); \
49 READ_WB_REG_CASE(OFF, 2, REG, T, VAL); \
50 READ_WB_REG_CASE(OFF, 3, REG, T, VAL); \
51 READ_WB_REG_CASE(OFF, 4, REG, T, VAL); \
[all...]
/linux-master/arch/x86/kernel/
H A Dalternative.c2368 atomic_cond_read_acquire(&bp_desc.refs, !VAL);
/linux-master/drivers/accel/ivpu/
H A Divpu_mmu.c441 return REGV_POLL_FLD(IVPU_MMU_REG_CR0ACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US);
448 return REGV_POLL_FLD(IVPU_MMU_REG_IRQ_CTRLACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US);
468 ret = REGV_POLL_FLD(IVPU_MMU_REG_CMDQ_CONS, VAL, cmdq->prod,
/linux-master/drivers/comedi/drivers/
H A Ds626.h447 #define S626_I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
448 #define S626_I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
449 #define S626_I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
/linux-master/drivers/gpio/
H A Dgpio-it87.c38 #define VAL 0x2f macro
95 outb(0x02, VAL);
102 outb(ldn, VAL);
108 return inb(VAL);
114 outb(val, VAL);
122 val = inb(VAL) << 8;
124 val |= inb(VAL);
/linux-master/drivers/gpu/drm/panel/
H A Dpanel-novatek-nt39016.c70 #define RV(REG, VAL) { .reg = (REG), .def = (VAL), .delay_us = 2 }
/linux-master/drivers/hwmon/
H A Dsmsc47b397.c42 #define VAL 0x2f /* The value to read/write */ macro
47 outb(val, VAL);
53 return inb(VAL);
H A Dsmsc47m1.c44 #define VAL 0x2f /* The value to read/write */ macro
50 outb(val, VAL);
57 return inb(VAL);
/linux-master/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.c463 val = atomic_cond_read_relaxed(&cmdq->lock, VAL >= 0);
576 atomic_long_cond_read_relaxed(ptr, (VAL & mask) == valid);
648 smp_cond_load_relaxed(cmd, !VAL || (ret = queue_poll(&qp)));
815 atomic_cond_read_relaxed(&cmdq->owner_prod, VAL == llq.prod);
/linux-master/drivers/net/ethernet/freescale/fs_enet/
H A Dmac-fcc.c72 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
H A Dmii-fec.c49 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
/linux-master/drivers/net/ethernet/huawei/hinic/
H A Dhinic_hw_cmdq.c625 errcode = CMDQ_WQE_ERRCODE_GET(be32_to_cpu(status->status_info), VAL);
/linux-master/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic.h880 #define QLCNIC_IS_LB_CONFIGURED(VAL) \
881 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
H A Dqlcnic_83xx_hw.h405 #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2)))
406 #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2))
H A Dqlcnic_hdr.h641 #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4)))
642 #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4)))
643 #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4)))
644 #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4)))
645 #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL)
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