Searched refs:L1 (Results 1 - 25 of 42) sorted by path

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/linux-master/arch/arm/mach-omap2/
H A Dsram242x.S39 str r3, [r2] @ go to L1-freq operation
42 mov r9, #0x1 @ set up for L1 voltage call
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
105 str r5, [r4] @ Force transition to L1
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
200 str r8, [r10] @ Force transition to L1
H A Dsram243x.S39 str r3, [r2] @ go to L1-freq operation
42 mov r9, #0x1 @ set up for L1 voltage call
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
105 str r5, [r4] @ Force transition to L1
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
200 str r8, [r10] @ Force transition to L1
H A Dsleep44xx.S47 * 1 - CPUx L1 and logic lost: MPUSS CSWR
48 * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
49 * 3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
67 * Flush all data from the L1 data cache before disabling
75 mov r1, #0xFF @ clean seucre L1
/linux-master/arch/hexagon/lib/
H A Dmemset.S159 if (r2==#0) jump:nt .L1
186 if (p1) jump .L1
197 if (p0.new) jump:nt .L1
208 if (p0.new) jump:nt .L1
284 .L1:
/linux-master/arch/m68k/fpsp040/
H A Dsetox.S104 | 3.1 R := X + N*L1, where L1 := single-precision(-log2/64).
105 | 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
108 | b) N*L1 is exact because N is no longer than 22 bits and
109 | L1 is no longer than 24 bits.
110 | c) The calculation X+N*L1 is also exact due to cancellation.
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
241 | 3.1 R := X + N*L1, wher
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/linux-master/arch/m68k/ifpsp060/src/
H A Dfplsp.S6758 # 3.1 R := X + N*L1, #
6759 # where L1 := single-precision(-log2/64). #
6761 # L2 := extended-precision(-log2/64 - L1).#
6762 # Notes: a) The way L1 and L2 are chosen ensures L1+L2 #
6764 # b) N*L1 is exact because N is no longer than 22 bits #
6765 # and L1 is no longer than 24 bits. #
6766 # c) The calculation X+N*L1 is also exact due to #
6767 # cancellation. Thus, R is practically X+N(L1+L2) to full #
6904 # 3.1 R := X + N*L1, #
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H A Dfpsp.S6864 # 3.1 R := X + N*L1, #
6865 # where L1 := single-precision(-log2/64). #
6867 # L2 := extended-precision(-log2/64 - L1).#
6868 # Notes: a) The way L1 and L2 are chosen ensures L1+L2 #
6870 # b) N*L1 is exact because N is no longer than 22 bits #
6871 # and L1 is no longer than 24 bits. #
6872 # c) The calculation X+N*L1 is also exact due to #
6873 # cancellation. Thus, R is practically X+N(L1+L2) to full #
7010 # 3.1 R := X + N*L1, #
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/linux-master/arch/sparc/lib/
H A DM7memcpy.S64 * prefetch src data to L2 cache; let HW prefetch move data to L1 cache
82 * align dst on 64 byte boundary; prefetch src data to L1 cache
436 ! Gives existing cache lines time to be moved out of L1/L2/L3 cache.
/linux-master/arch/sparc/net/
H A Dbpf_jit_64.h21 #define L1 0x11 macro
/linux-master/arch/alpha/boot/
H A Dbootp.c59 * code has the L1 page table identity-map itself in the second PTE
60 * in the L1 page table. Thus the L1-page is virtually addressable
65 #define L1 ((unsigned long *) 0x200802000) macro
77 pcb_va->ptbr = L1[1] >> 32;
H A Dbootpz.c108 * code has the L1 page table identity-map itself in the second PTE
109 * in the L1 page table. Thus the L1-page is virtually addressable
113 #define L1 ((unsigned long *) 0x200802000) macro
125 pcb_va->ptbr = L1[1] >> 32;
H A Dmain.c53 * code has the L1 page table identity-map itself in the second PTE
54 * in the L1 page table. Thus the L1-page is virtually addressable
59 #define L1 ((unsigned long *) 0x200802000) macro
71 pcb_va->ptbr = L1[1] >> 32;
/linux-master/arch/alpha/lib/
H A Dev6-clear_user.S20 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
139 wh64 ($3) # .. .. .. L1 : memory subsystem hint
H A Dev6-memcpy.S18 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
85 wh64 ($7) # L1 : memory subsystem hint: 64 bytes at
H A Dev6-memset.S17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
161 wh64 ($4) # L1 : memory subsystem write hint
339 wh64 ($4) # L1 : memory subsystem write hint
527 wh64 ($4) # L1 : memory subsystem write hint
/linux-master/arch/arc/kernel/
H A Dentry-compact.S152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
155 ; -L1 IRQ taken
156 ; -L2 interrupts L1 (before L1 ISR could run)
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
161 ; while prev L1 is still unserviced
165 ; L2 interrupting L1 implie
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/linux-master/arch/arm/mm/
H A Dcache-v7.S31 * the L1; however, the L1 comes out of reset in an undefined state, so
43 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR
190 * working outwards from L1 cache. This is done using Set/Way based cache
H A Dproc-macros.S271 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
H A Dproc-v7.S84 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
445 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
451 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
H A Dproc-xsc3.S41 * The cache line size of the L1 I, L1 D and unified L2 cache.
46 * The size of the L1 D cache.
62 * This macro cleans and invalidates the entire L1 D cache.
68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
224 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1
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/linux-master/arch/m68k/lib/
H A Ddivsi3.S95 jpl L1
102 L1: movel sp@(8), d0 /* d0 = dividend */ label
H A Dudivsi3.S144 L1: addl d0,d0 | shift reg pair (p,a) one bit left label
152 jcc L1
/linux-master/arch/powerpc/perf/
H A Dgeneric-compat-pmu.c32 /* Instruction ERAT/L1-TLB miss */
46 /* Data ERAT/L1-TLB miss/reload */
52 /* L1 Dcache reload from memory */
54 /* L1 Dcache store miss */
64 /* L1 Dcache load miss */
109 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
110 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
111 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
H A Disa207-common.c223 ret = PH(LVL, L1) | LEVEL(L1) | P(SNOOP, HIT);
301 ret = PM(LVL, L1);
H A Dpower10-pmu.c29 * | | | *- L1/L2/L3 cache_sel | |*-radix_scope_qual
133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
135 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS);
136 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
137 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
138 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
139 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ);

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