Searched refs:xge_wr_csr (Results 1 - 6 of 6) sorted by relevance
/linux-master/drivers/net/ethernet/apm/xgene-v2/ |
H A D | enet.c | 12 void xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val) function 32 xge_wr_csr(pdata, ENET_CLKEN, 0x3); 33 xge_wr_csr(pdata, ENET_SRST, 0xf); 34 xge_wr_csr(pdata, ENET_SRST, 0); 35 xge_wr_csr(pdata, CFG_MEM_RAM_SHUTDOWN, 1); 36 xge_wr_csr(pdata, CFG_MEM_RAM_SHUTDOWN, 0); 48 xge_wr_csr(pdata, ENET_SHIM, DEVM_ARAUX_COH | DEVM_AWAUX_COH); 57 xge_wr_csr(pdata, CFG_FORCE_LINK_STATUS_EN, 1); 58 xge_wr_csr(pdata, FORCE_LINK_STATUS, 1); 60 xge_wr_csr(pdat [all...] |
H A D | mac.c | 14 xge_wr_csr(pdata, MAC_CONFIG_1, SOFT_RESET); 15 xge_wr_csr(pdata, MAC_CONFIG_1, 0); 58 xge_wr_csr(pdata, MAC_CONFIG_2, mc2); 59 xge_wr_csr(pdata, INTERFACE_CONTROL, intf_ctrl); 60 xge_wr_csr(pdata, RGMII_REG_0, rgmii); 61 xge_wr_csr(pdata, ICM_CONFIG0_REG_0, icm0); 62 xge_wr_csr(pdata, ICM_CONFIG2_REG_0, icm2); 63 xge_wr_csr(pdata, ECM_CONFIG0_REG_0, ecm0); 75 xge_wr_csr(pdata, STATION_ADDR0, addr0); 76 xge_wr_csr(pdat [all...] |
H A D | ring.c | 39 xge_wr_csr(pdata, DMATXDESCL, dma_addr); 40 xge_wr_csr(pdata, DMATXDESCH, upper_32_bits(dma_addr)); 51 xge_wr_csr(pdata, DMARXDESCL, dma_addr); 52 xge_wr_csr(pdata, DMARXDESCH, upper_32_bits(dma_addr)); 63 xge_wr_csr(pdata, DMAINTRMASK, data); 68 xge_wr_csr(pdata, DMAINTRMASK, 0);
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H A D | enet.h | 28 void xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val);
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H A D | mdio.c | 20 xge_wr_csr(pdata, MII_MGMT_ADDRESS, val); 22 xge_wr_csr(pdata, MII_MGMT_CONTROL, data); 44 xge_wr_csr(pdata, MII_MGMT_ADDRESS, val); 46 xge_wr_csr(pdata, MII_MGMT_COMMAND, MII_READ_CYCLE); 58 xge_wr_csr(pdata, MII_MGMT_COMMAND, 0);
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H A D | main.c | 220 xge_wr_csr(pdata, DMATXCTRL, 1); 274 xge_wr_csr(pdata, DMATXSTATUS, 1); 336 xge_wr_csr(pdata, DMARXSTATUS, 1); 337 xge_wr_csr(pdata, DMARXCTRL, 1); 485 xge_wr_csr(pdata, DMARXCTRL, 1); 591 xge_wr_csr(pdata, DMATXCTRL, 0); 594 xge_wr_csr(pdata, DMATXSTATUS, ~0U);
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