Searched refs:writew (Results 1 - 25 of 319) sorted by relevance

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/linux-master/arch/m68k/include/asm/
H A Dvga.h27 #undef writew macro
34 #define writew raw_outw macro
H A Dio_no.h81 #define writew writew macro
82 static inline void writew(u16 value, volatile void __iomem *addr) function
105 #define writew __raw_writew macro
/linux-master/arch/m68k/coldfire/
H A Dnettel.c109 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
110 writew(macp[0], ioaddr + SMC91xx_BASEMAC);
111 writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2);
112 writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4);
125 writew(0x00ec, MCFSIM_PADDR);
127 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
128 writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR);
132 writew(0x1180, MCFSIM_CSCR3);
H A Dm527x.c61 writew(par, MCFGPIO_PAR_TIMER);
64 writew(0x003e, MCFGPIO_PAR_QSPI);
89 writew(par, MCFGPIO_PAR_FECI2C);
105 writew(sepmask, MCFGPIO_PAR_UART);
122 writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
128 writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
/linux-master/drivers/pwm/
H A Dpwm-ep93xx.c74 writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
88 writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_INVERT);
90 writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_INVERT);
97 writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
129 writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT);
130 writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE);
132 writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE);
133 writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT);
151 writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
/linux-master/sound/isa/msnd/
H A Dmsnd.c46 writew(PCTODSP_BASED(start), base + JQS_wStart);
47 writew(PCTODSP_OFFSET(size) - 1, base + JQS_wSize);
48 writew(0, base + JQS_wHead);
49 writew(0, base + JQS_wTail);
266 writew(PCTODSP_BASED(offset), pDAQ);
269 writew(wTmp, chip->DARQ + JQS_wTail);
318 writew(chip->play_period_bytes, DAQD + DAQDS_wSize);
327 writew(PCTODSP_BASED(offset), DAQD + DAQDS_wStart);
339 writew(DAPQ_tail, chip->DAPQ + JQS_wTail);
365 writew(PCTODSP_OFFSE
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/linux-master/drivers/i2c/busses/
H A Di2c-wmt.c138 writew(0, i2c_dev->base + REG_CDR);
140 writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
147 writew(val, i2c_dev->base + REG_CR);
154 writew(tcr_val, i2c_dev->base + REG_TCR);
159 writew(val, i2c_dev->base + REG_CR);
177 writew(val, i2c_dev->base + REG_CR);
183 writew(CR_ENABLE, i2c_dev->base + REG_CR);
185 writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
187 writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
209 writew(va
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/linux-master/drivers/scsi/arm/
H A Dcumana_1.c64 v=*laddr++; writew(L(v), dma); writew(H(v), dma);
65 v=*laddr++; writew(L(v), dma); writew(H(v), dma);
66 v=*laddr++; writew(L(v), dma); writew(H(v), dma);
67 v=*laddr++; writew(L(v), dma); writew(H(v), dma);
68 v=*laddr++; writew(L(v), dma); writew(
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/linux-master/arch/arm/mach-mstar/
H A Dmstarv7.c94 writew(bootaddr & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_LOW);
95 writew((bootaddr >> 16) & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_HIGH);
98 writew(MSTARV7_CPU1_UNLOCK_MAGIC, smpctrl + MSTARV7_CPU1_UNLOCK);
/linux-master/drivers/comedi/drivers/
H A Dicp_multi.c120 writew(adc_csr, dev->mmio + ICP_MULTI_ADC_CSR);
124 writew(adc_csr | ICP_MULTI_ADC_CSR_ST,
166 writew(dac_csr, dev->mmio + ICP_MULTI_DAC_CSR);
177 writew(val, dev->mmio + ICP_MULTI_AO);
180 writew(dac_csr | ICP_MULTI_DAC_CSR_ST,
205 writew(s->state, dev->mmio + ICP_MULTI_DO);
217 writew(0, dev->mmio + ICP_MULTI_INT_EN);
218 writew(ICP_MULTI_INT_MASK, dev->mmio + ICP_MULTI_INT_STAT);
225 writew(dac_csr, dev->mmio + ICP_MULTI_DAC_CSR);
228 writew(
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H A Ddt3000.c231 writew(cmd, dev->mmio + DPR_CMD_MBX);
250 writew(subsys, dev->mmio + DPR_SUBSYS);
252 writew(chan, dev->mmio + DPR_PARAMS(0));
253 writew(gain, dev->mmio + DPR_PARAMS(1));
263 writew(subsys, dev->mmio + DPR_SUBSYS);
265 writew(chan, dev->mmio + DPR_PARAMS(0));
266 writew(0, dev->mmio + DPR_PARAMS(1));
267 writew(data, dev->mmio + DPR_PARAMS(2));
298 writew(rear, dev->mmio + DPR_AD_BUF_REAR);
304 writew(DPR_SUBSYS_A
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H A Dme_daq.c176 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
194 writew((s->state & 0xffff), mmio_porta);
196 writew(((s->state >> 16) & 0xffff), mmio_portb);
251 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
253 writew(0x00, dev->mmio + ME_STATUS_REG); /* clear interrupts */
257 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
265 writew(val, dev->mmio + ME_AI_FIFO_REG);
269 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG);
289 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG);
307 writew(devpri
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/linux-master/arch/arm/mach-spear/
H A Dtime.c75 writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
81 writew(0xFFFF, gpt_base + LOAD(CLKSRC));
86 writew(val, gpt_base + CR(CLKSRC));
99 writew(val, gpt_base + CR(CLKEVT));
118 writew(val, gpt_base + CR(CLKEVT));
133 writew(period, gpt_base + LOAD(CLKEVT));
138 writew(val, gpt_base + CR(CLKEVT));
160 writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));
162 writew(cycles, gpt_base + LOAD(CLKEVT));
165 writew(va
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/linux-master/drivers/watchdog/
H A Drza_wdt.c79 writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
83 writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);
87 writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR);
88 writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT);
89 writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME |
99 writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
108 writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT);
128 writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
132 writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);
138 writew(WRCSR_MAGI
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H A Dmsc313e_wdt.c46 writew(timeout & 0xffff, priv->base + REG_WDT_MAX_PRD_L);
47 writew((timeout >> 16) & 0xffff, priv->base + REG_WDT_MAX_PRD_H);
48 writew(1, priv->base + REG_WDT_CLR);
56 writew(1, priv->base + REG_WDT_CLR);
64 writew(0, priv->base + REG_WDT_MAX_PRD_L);
65 writew(0, priv->base + REG_WDT_MAX_PRD_H);
66 writew(0, priv->base + REG_WDT_CLR);
/linux-master/drivers/rtc/
H A Drtc-ssd202d.c104 writew(val | field, priv->base + reg);
106 writew(val & ~field, priv->base + reg);
121 writew(val | field, priv->base + reg);
122 writew(base, priv->base + REG_WRDATA_L);
123 writew(base >> 16, priv->base + REG_WRDATA_H);
125 writew(val & ~field, priv->base + reg);
134 writew(val | CNT_RD_BIT, priv->base + REG_CTRL1);
136 writew(val & ~CNT_RD_BIT, priv->base + REG_CTRL1);
139 writew(val | CNT_RD_TRIG_BIT, priv->base + REG_CNT_TRIG);
140 writew(va
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H A Drtc-msc313.c76 writew(reg, priv->rtc_base + REG_RTC_CTRL);
86 writew((seconds & 0xFFFF), priv->rtc_base + REG_RTC_MATCH_VAL_L);
87 writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_MATCH_VAL_H);
105 writew(reg, priv->rtc_base + REG_RTC_CTRL);
118 writew(reg | READ_EN_BIT, priv->rtc_base + REG_RTC_CTRL);
139 writew(seconds & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_L);
140 writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_H);
144 writew(reg | LOAD_EN_BIT, priv->rtc_base + REG_RTC_CTRL);
173 writew(reg, priv->rtc_base + REG_RTC_CTRL);
222 writew(rat
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H A Drtc-mxc.c136 writew(day, ioaddr + RTC_DAYR);
137 writew(sec, ioaddr + RTC_SECOND);
138 writew(temp, ioaddr + RTC_HOURMIN);
141 writew(day, ioaddr + RTC_DAYALARM);
142 writew(sec, ioaddr + RTC_ALRM_SEC);
143 writew(temp, ioaddr + RTC_ALRM_HM);
161 writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
181 writew(reg, ioaddr + RTC_RTCIENR);
197 writew(status, ioaddr + RTC_RTCISR);
361 writew(re
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/linux-master/drivers/input/keyboard/
H A Dimx_keypad.c96 writew(reg_val, keypad->mmio_base + KPDR);
100 writew(reg_val, keypad->mmio_base + KPCR);
106 writew(reg_val, keypad->mmio_base + KPCR);
115 writew(reg_val, keypad->mmio_base + KPDR);
137 writew(reg_val, keypad->mmio_base + KPDR);
261 writew(reg_val, keypad->mmio_base + KPSR);
266 writew(reg_val, keypad->mmio_base + KPSR);
279 writew(reg_val, keypad->mmio_base + KPSR);
284 writew(reg_val, keypad->mmio_base + KPSR);
299 writew(reg_va
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/linux-master/drivers/gpu/drm/nouveau/dispnv50/
H A Dheadc57d.c151 writew(r + ri * i, mem + 0);
152 writew(g + gi * i, mem + 2);
153 writew(b + bi * i, mem + 4);
160 writew(readw(mem - 8), mem + 0);
161 writew(readw(mem - 6), mem + 2);
162 writew(readw(mem - 4), mem + 4);
172 writew(drm_color_lut_extract(in-> red, 16), mem + 0);
173 writew(drm_color_lut_extract(in->green, 16), mem + 2);
174 writew(drm_color_lut_extract(in-> blue, 16), mem + 4);
180 writew(read
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/linux-master/drivers/media/pci/netup_unidvb/
H A Dnetup_unidvb_spi.c85 writew(reg | NETUP_SPI_CTRL_IRQ, &spi->regs->control_stat);
87 writew(reg & ~NETUP_SPI_CTRL_IMASK, &spi->regs->control_stat);
105 writew(NETUP_SPI_CTRL_LAST_CS, &spi->regs->control_stat);
106 writew(0, &spi->regs->control_stat);
129 writew((frag_size & 0x3ff) |
195 writew(2, &nspi->regs->clock_divider);
196 writew(NETUP_UNIDVB_IRQ_SPI, ndev->bmmio0 + REG_IMASK_SET);
233 writew(reg | NETUP_SPI_CTRL_IRQ, &spi->regs->control_stat);
235 writew(reg & ~NETUP_SPI_CTRL_IMASK, &spi->regs->control_stat);
H A Dnetup_unidvb_i2c.c73 writew(reg & ~TWI_IRQEN, &i2c->regs->twi_ctrl0_stat);
96 writew(tmp & ~FIFO_IRQEN, &i2c->regs->rx_fifo.stat_ctrl);
104 writew(tmp & ~FIFO_IRQEN, &i2c->regs->tx_fifo.stat_ctrl);
123 writew(TWI_SOFT_RESET, &i2c->regs->twi_addr_ctrl1);
124 writew(TWI_CLKDIV, &i2c->regs->clkdiv);
125 writew(FIFO_RESET, &i2c->regs->tx_fifo.stat_ctrl);
126 writew(FIFO_RESET, &i2c->regs->rx_fifo.stat_ctrl);
127 writew(0x800, &i2c->regs->tx_fifo.stat_ctrl);
128 writew(0x800, &i2c->regs->rx_fifo.stat_ctrl);
148 writew(read
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/linux-master/arch/csky/include/asm/
H A Dio.h26 #define writew(v,c) ({ wmb(); writew_relaxed((v),(c)); }) macro
30 #define writew(v,c) ({ wmb(); writew_relaxed((v),(c)); mb(); }) macro
/linux-master/drivers/phy/renesas/
H A Dphy-rcar-gen3-usb3.c65 writew(val, r->base + USB30_CLKSET1);
88 writew(val, r->base + USB30_SSC_SET);
96 writew(CLKSET0_PRIVATE | CLKSET0_USB30_FSEL_USB_EXTAL,
98 writew(PHY_ENABLE_RESET_EN, r->base + USB30_PHY_ENABLE);
115 writew(VBUS_EN_VBUS_EN, r->base + USB30_VBUS_EN);
/linux-master/drivers/tty/serial/
H A Dmilbeaut_usio.c67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
85 writew(port->x_char, port->membase + MLB_USIO_REG_DR);
99 writew(xmit->buf[xmit->tail], port->membase + MLB_USIO_REG_DR);
107 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FDRQ,
124 writew(fcr | MLB_USIO_FCR_FTIE, port->membase + MLB_USIO_REG_FCR);
198 writew(readw(port->membase + MLB_USIO_REG_FCR) |
275 writew(0, port->membase + MLB_USIO_REG_FCR);
276 writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2,
278 writew(MLB_USIO_FCR_FE
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