Searched refs:vulp (Results 1 - 10 of 10) sorted by relevance

/linux-master/arch/alpha/kernel/
H A Dcore_t2.c192 t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
193 *(vulp)T2_HAE_3 = 0x40000000UL | t2_cfg;
227 *(vulp)T2_HAE_3 = t2_cfg;
244 t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
245 *(vulp)T2_HAE_3 = t2_cfg | 0x40000000UL;
278 *(vulp)T2_HAE_3 = t2_cfg;
335 *(vulp)T2_WBASE1 = temp | 0x80000UL; /* OR in ENABLE bit */
337 *(vulp)T2_WMASK1 = temp;
338 *(vulp)T2_TBASE1 = 0;
342 __func__, *(vulp)T2_WBASE
[all...]
H A Dirq_pyxis.c27 *(vulp)PYXIS_INT_MASK = mask;
29 *(vulp)PYXIS_INT_MASK;
51 *(vulp)PYXIS_INT_MASK = mask;
54 *(vulp)PYXIS_INT_REQ = bit;
57 *(vulp)PYXIS_INT_MASK;
74 pld = *(vulp)PYXIS_INT_REQ;
96 *(vulp)PYXIS_INT_MASK = 0; /* disable all */
97 *(vulp)PYXIS_INT_REQ = -1; /* flush all */
H A Dsys_ruffian.c39 *(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb();
40 *(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */
189 bank = *(vulp)bank_addr;
H A Dsys_miata.c69 *(vulp)PYXIS_INT_HILO = 0x000000B2UL; mb(); /* ISA/NMI HI */
70 *(vulp)PYXIS_RT_COUNT = 0UL; mb(); /* clear count */
H A Dproto.h12 #define vulp volatile unsigned long * macro
H A Dsetup.c1245 sc_ctl = *(vulp) phys_to_virt (0xfffff000a8UL);
1278 cbox_config = *(vulp) phys_to_virt (0xfffff00008UL);
H A Dcore_cia.c802 pyxis_cc = *(vulp)PYXIS_RT_COUNT;
803 do { } while(*(vulp)PYXIS_RT_COUNT - pyxis_cc < 4096);
/linux-master/arch/alpha/include/asm/
H A Dcore_cia.h343 #define vulp volatile unsigned long __force * macro
428 return *(vulp)addr;
436 *(vulp)addr = b;
483 #undef vulp macro
H A Dcore_mcpcia.h251 #define vulp volatile unsigned long __force * macro
346 return *(vulp)addr;
356 *(vulp)addr = b;
386 #undef vulp macro
H A Dcore_t2.h355 #define vulp volatile unsigned long * macro
400 return *(vulp) ((addr << 5) + T2_IO + 0x18);
405 *(vulp) ((addr << 5) + T2_IO + 0x18) = b;
603 #undef vulp macro

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