alpha/kernel/core_t2.c

192 		t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
193 		*(vulp)T2_HAE_3 = 0x40000000UL | t2_cfg;
227 		*(vulp)T2_HAE_3 = t2_cfg;
244 		t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
245 		*(vulp)T2_HAE_3 = t2_cfg | 0x40000000UL;
278 		*(vulp)T2_HAE_3 = t2_cfg;
335 	*(vulp)T2_WBASE1 = temp | 0x80000UL; /* OR in ENABLE bit */
337 	*(vulp)T2_WMASK1 = temp;
338 	*(vulp)T2_TBASE1 = 0;
342 	       __func__, *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);
359 	*(vulp)T2_WBASE2 = temp | 0xc0000UL; /* OR in ENABLE/SG bits */
361 	*(vulp)T2_WMASK2 = temp;
362 	*(vulp)T2_TBASE2 = virt_to_phys(hose->sg_isa->ptes) >> 1;
369 	       __func__, *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);
378 	printk("%s: HAE_2 was 0x%lx\n", __func__, *(vulp)T2_HAE_2);
379 	printk("%s: HAE_3 was 0x%lx\n", __func__, *(vulp)T2_HAE_3);
380 	printk("%s: HAE_4 was 0x%lx\n", __func__, *(vulp)T2_HAE_4);
381 	printk("%s: HBASE was 0x%lx\n", __func__, *(vulp)T2_HBASE);
384 	       *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);
386 	       *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);
392 	t2_saved_config.window[0].wbase = *(vulp)T2_WBASE1;
393 	t2_saved_config.window[0].wmask = *(vulp)T2_WMASK1;
394 	t2_saved_config.window[0].tbase = *(vulp)T2_TBASE1;
395 	t2_saved_config.window[1].wbase = *(vulp)T2_WBASE2;
396 	t2_saved_config.window[1].wmask = *(vulp)T2_WMASK2;
397 	t2_saved_config.window[1].tbase = *(vulp)T2_TBASE2;
400 	t2_saved_config.hae_2 = *(vulp)T2_HAE_2;
401 	t2_saved_config.hae_3 = *(vulp)T2_HAE_3;
402 	t2_saved_config.hae_4 = *(vulp)T2_HAE_4;
403 	t2_saved_config.hbase = *(vulp)T2_HBASE;
422 	temp = *(vulp)T2_IOCSR;
426 		*(vulp)T2_IOCSR = temp | (0x1UL << 26);
428 		*(vulp)T2_IOCSR; /* read it back to make sure */
464 	*(vulp)T2_HBASE = 0x0; /* Disable HOLES. */
467 	*(vulp)T2_HAE_1 = 0; mb(); /* Sparse MEM HAE */
468 	*(vulp)T2_HAE_2 = 0; mb(); /* Sparse I/O HAE */
469 	*(vulp)T2_HAE_3 = 0; mb(); /* Config Space HAE */
480 	*(vulp)T2_HAE_4 = 0; mb();
489 	*(vulp)T2_WBASE1 = t2_saved_config.window[0].wbase;
490 	*(vulp)T2_WMASK1 = t2_saved_config.window[0].wmask;
491 	*(vulp)T2_TBASE1 = t2_saved_config.window[0].tbase;
492 	*(vulp)T2_WBASE2 = t2_saved_config.window[1].wbase;
493 	*(vulp)T2_WMASK2 = t2_saved_config.window[1].wmask;
494 	*(vulp)T2_TBASE2 = t2_saved_config.window[1].tbase;
497 	*(vulp)T2_HAE_1 = srm_hae;
498 	*(vulp)T2_HAE_2 = t2_saved_config.hae_2;
499 	*(vulp)T2_HAE_3 = t2_saved_config.hae_3;
500 	*(vulp)T2_HAE_4 = t2_saved_config.hae_4;
501 	*(vulp)T2_HBASE = t2_saved_config.hbase;
503 	*(vulp)T2_HBASE; /* READ it back to ensure WRITE occurred. */
511 	t2_iocsr = *(vulp)T2_IOCSR;
514 	*(vulp)T2_IOCSR = t2_iocsr | (0x1UL << 28);
516 	*(vulp)T2_IOCSR; /* read it back to make sure */
519 	*(vulp)T2_IOCSR = t2_iocsr & ~(0x1UL << 28);
521 	*(vulp)T2_IOCSR; /* read it back to make sure */
541 	*(vulp)T2_CERR1 |= *(vulp)T2_CERR1;
542 	*(vulp)T2_PERR1 |= *(vulp)T2_PERR1;