Searched refs:v3_mem_type (Results 1 - 3 of 3) sorted by relevance

/haiku/headers/private/graphics/matrox/
H A DDriverInterface.h236 uint8 v3_mem_type; /* pins v3 memory type info */ member in struct:__anon785::__anon789
/haiku/src/add-ons/accelerants/matrox/engine/
H A Dmga_info.c140 si->ps.v3_mem_type = 0;
243 si->ps.v3_mem_type = pins[54];
281 /* the rest of the OPTION info for pins v3 comes via 'v3_clk_div' and 'v3_mem_type'. */
446 si->ps.v3_mem_type = 0;
552 si->ps.v3_mem_type = 0;
614 si->ps.v3_mem_type = 0;
993 LOG(2,("v3_mem_type: $%02x\n", si->ps.v3_mem_type));
H A Dmga_general.c359 * - b3 v3_mem_type was included by Mark for memconfig setup: but looks like not defined */
360 CFGW(OPTION,(CFGR(OPTION)&0xFFFF8FFF) | ((si->ps.v3_mem_type & 0x04) << 10));
362 * - Mark says: if((v3_mem_type & 0x03) == 0x03) then do not or-in bits in option2;
363 * but looks like v3_mem_type b1 is not defined,
364 * - Mark also says: place v3_mem_type b1 in option2 bit13 (if not 0x03) but b13 = reserved. */
365 CFGW(OPTION2,(CFGR(OPTION2)&0xFFFFCFFF)|((si->ps.v3_mem_type & 0x01) << 12));
367 CFGW(OPTION2,(CFGR(OPTION2)&0xFFFFFFF0) | ((si->ps.v3_mem_type & 0xf0) >> 4));
462 CFGW(OPTION,(CFGR(OPTION)&0xFFFF83FF) | ((si->ps.v3_mem_type & 0x07) << 10));

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