Searched refs:v3_clk_div (Results 1 - 4 of 4) sorted by relevance

/haiku/src/add-ons/accelerants/matrox/engine/
H A Dmga_info.c139 si->ps.v3_clk_div = 0;
242 si->ps.v3_clk_div = pins[52];
281 /* the rest of the OPTION info for pins v3 comes via 'v3_clk_div' and 'v3_mem_type'. */
293 si->ps.sdram = (si->ps.v3_clk_div & 0x10);
445 si->ps.v3_clk_div = 0;
551 si->ps.v3_clk_div = 0;
613 si->ps.v3_clk_div = 0;
992 LOG(2,("v3_clock_div: $%02x\n", si->ps.v3_clk_div));
H A Dmga_dac.c1111 if (si->ps.v3_clk_div & 0x01) temp |= 0x08;
1112 if (si->ps.v3_clk_div & 0x02) temp |= 0x10;
1113 if (si->ps.v3_clk_div & 0x04) temp |= 0x80;
1116 //if (si->ps.v3_clk_div & 0x08) temp |= 0x40;
1175 if (si->ps.v3_clk_div & 0x01) temp |= 0x08;
1176 if (si->ps.v3_clk_div & 0x02) temp |= 0x10;
1179 //if (si->ps.v3_clk_div & 0x08) temp |= 0x40;
H A Dmga_crtc.c469 if (si->ps.v3_clk_div & 0x02)
/haiku/headers/private/graphics/matrox/
H A DDriverInterface.h235 uint8 v3_clk_div; /* pins v3 memory and system clock division factors */ member in struct:__anon785::__anon789

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