| /linux-master/arch/arm64/include/asm/ |
| H A D | mmu_context.h | 44 unsigned long ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); local
46 write_sysreg(ttbr, ttbr0_el1);
185 u64 ttbr; local
191 ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir));
193 ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48;
195 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr);
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| H A D | uaccess.h | 61 unsigned long flags, ttbr; local
64 ttbr = read_sysreg(ttbr1_el1);
65 ttbr &= ~TTBR_ASID_MASK;
67 write_sysreg(ttbr - RESERVED_SWAPPER_OFFSET, ttbr0_el1);
69 write_sysreg(ttbr, ttbr1_el1);
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| H A D | assembler.h | 464 * in the tlb, switch the ttbr to a zero page when we invalidate the old
587 * ttbr: Value of ttbr to set, modified.
589 .macro offset_ttbr1, ttbr, tmp variable
594 orr \tmp, \ttbr, #TTBR1_BADDR_4852_OFFSET variable
595 csel \ttbr, \tmp, \ttbr, eq variable
604 * ttbr: returns the TTBR value
606 .macro phys_to_ttbr, ttbr, phys variable
608 orr \ttbr, \phy variable
609 and \\ttbr, \\ttbr, #TTBR_BADDR_MASK_52 variable
[all...] |
| /linux-master/arch/arm/include/asm/ |
| H A D | proc-fns.h | 158 u64 ttbr; \
160 : "=r" (ttbr)); \
161 ttbr; \
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| /linux-master/include/linux/ |
| H A D | io-pgtable.h | 130 u64 ttbr; member in struct:io_pgtable_cfg::__anon562::__anon563
156 u32 ttbr; member in struct:io_pgtable_cfg::__anon562::__anon567
168 u64 ttbr[4]; member in struct:io_pgtable_cfg::__anon562::__anon569
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| /linux-master/drivers/gpu/drm/msm/ |
| H A D | msm_mmu.h | 60 int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr,
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| H A D | msm_iommu.c | 27 phys_addr_t ttbr; member in struct:msm_iommu_pagetable
173 phys_addr_t *ttbr, int *asid)
182 if (ttbr)
183 *ttbr = pagetable->ttbr;
309 pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr;
172 msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr, int *asid) argument
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| /linux-master/drivers/iommu/arm/arm-smmu/ |
| H A D | arm-smmu-qcom.c | 156 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
168 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
169 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
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| H A D | arm-smmu.c | 498 cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr;
499 cb->ttbr[1] = 0;
501 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID,
503 cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID,
507 cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
509 cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
512 cb->ttbr[
[all...] |
| H A D | arm-smmu.h | 354 u64 ttbr[2]; member in struct:arm_smmu_cb
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| H A D | qcom_iommu.c | 281 pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
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| /linux-master/arch/arm64/kernel/pi/ |
| H A D | map_kernel.c | 135 static void noinline __section(".idmap.text") set_ttbr0_for_lpa2(u64 ttbr) argument
150 :: "r"(sctlr & ~SCTLR_ELx_M), "r"(ttbr), "r"(tcr), "r"(sctlr));
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| /linux-master/drivers/iommu/ |
| H A D | apple-dart.c | 147 #define DART_TTBR(dart, sid, idx) ((dart)->hw->ttbr + \
181 u64 ttbr; member in struct:apple_dart_hw
565 pgtbl_cfg->apple_dart_cfg.ttbr[i]);
1215 .ttbr = DART_T8020_TTBR,
1241 .ttbr = DART_T8020_USB4_TTBR,
1267 .ttbr = DART_T8020_TTBR,
1292 .ttbr = DART_T8110_TTBR,
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| H A D | ipmmu-vmsa.c | 366 u64 ttbr; local
370 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr;
371 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr);
372 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32);
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| H A D | io-pgtable-dart.c | 426 cfg->apple_dart_cfg.ttbr[i] = virt_to_phys(data->pgd[i]);
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| H A D | io-pgtable-arm-v7s.c | 873 cfg->arm_v7s_cfg.ttbr = paddr | upper_32_bits(paddr);
875 cfg->arm_v7s_cfg.ttbr = paddr | ARM_V7S_TTBR_S |
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| H A D | mtk_iommu.c | 755 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);
1496 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);
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| H A D | msm_iommu.c | 274 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr);
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| H A D | io-pgtable-arm.c | 911 cfg->arm_lpae_s1_cfg.ttbr = virt_to_phys(data->pgd);
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| /linux-master/drivers/iommu/arm/arm-smmu-v3/ |
| H A D | arm-smmu-v3-sva.c | 172 cd->ttbr = virt_to_phys(mm->pgd);
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| H A D | arm-smmu-v3.h | 586 u64 ttbr; member in struct:arm_smmu_ctx_desc
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| H A D | arm-smmu-v3.c | 1287 cdptr[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK);
2251 cd->ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
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| /linux-master/drivers/gpu/drm/msm/adreno/ |
| H A D | a6xx_gpu.c | 107 phys_addr_t ttbr; local
114 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))
130 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
133 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
144 OUT_RING(ring, lower_32_bits(ttbr));
145 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr));
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