| /linux-master/drivers/gpu/drm/i915/gt/ |
| H A D | intel_sseu.h | 39 /* Maximum number of EUs that can exist within a subslice or DSS. */
44 /* The maximum number of bits needed to express each subslice/DSS independently */
81 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
123 int subslice)
126 subslice >= sseu->max_subslices)
130 return test_bit(subslice, sseu->subslice_mask.xehp);
132 return sseu->subslice_mask.hsw[slice] & BIT(subslice);
122 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, int subslice) argument
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| H A D | intel_workarounds.c | 548 * Only consider slices where one, and only one, subslice has 7
1106 unsigned int slice, subslice; local
1113 * Before any MMIO read into slice/subslice specific registers, MCR
1124 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
1125 GEM_BUG_ON(!subslice);
1126 subslice--;
1132 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
1135 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr);
1234 unsigned int slice, unsigned int subslice)
1232 __set_mcr_steering(struct i915_wa_list *wal, i915_reg_t steering_reg, unsigned int slice, unsigned int subslice) argument
1253 __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, unsigned int slice, unsigned int subslice) argument
1268 unsigned int subslice; local
1299 unsigned long slice, subslice = 0, slice_mask = 0; local
[all...] |
| H A D | intel_sseu.c | 48 int subslice)
52 return sseu->eu_mask.xehp[subslice];
54 return sseu->eu_mask.hsw[slice][subslice];
58 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, argument
64 sseu->eu_mask.xehp[subslice] = eu_mask;
66 sseu->eu_mask.hsw[slice][subslice] = eu_mask;
119 * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
121 * @sseu: SSEU structure containing subslice mask to copy
123 * Copies the subslice mask to a userspace buffer in the format expected by
374 * CHV supports subslice powe
47 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, int subslice) argument
[all...] |
| H A D | intel_engine_cs.c | 1805 int subslice; local
1826 for_each_ss_steering(iter, engine->gt, slice, subslice) {
1827 instdone->sampler[slice][subslice] =
1830 slice, subslice);
1831 instdone->row[slice][subslice] =
1834 slice, subslice);
1838 for_each_ss_steering(iter, engine->gt, slice, subslice)
1839 instdone->geom_svg[slice][subslice] =
1842 slice, subslice);
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| H A D | intel_gt_regs.h | 76 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
81 #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
509 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
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| /linux-master/drivers/gpu/drm/i915/ |
| H A D | i915_gpu_error.c | 443 int subslice; local
458 for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
460 slice, subslice,
461 ee->instdone.sampler[slice][subslice]);
463 for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
465 slice, subslice,
466 ee->instdone.row[slice][subslice]);
472 for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
474 slice, subslice,
475 ee->instdone.geom_svg[slice][subslice]);
[all...] |
| /linux-master/drivers/gpu/drm/i915/gt/uc/ |
| H A D | intel_guc_capture.c | 300 int slice, subslice, iter, i, num_steer_regs, num_tot_regs = 0; local
320 for_each_ss_steering(iter, gt, slice, subslice)
337 for_each_ss_steering(iter, gt, slice, subslice) {
339 __fill_ext_reg(extarray, &gen8_extregs[i], slice, subslice);
345 __fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice);
367 * For certain engine classes, there are slice and subslice
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| /linux-master/drivers/gpu/drm/xe/regs/ |
| H A D | xe_gt_regs.h | 54 #define MCR_SUBSLICE(subslice) REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice)
|