Searched refs:sparc_config (Results 1 - 9 of 9) sorted by relevance

/linux-master/arch/sparc/kernel/
H A Dtime_32.c92 sparc_config.clear_clock_irq();
95 sparc_config.clear_clock_irq();
132 ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
146 offset += sparc_config.cs_period;
160 offset = sparc_config.get_cycles_offset();
164 cycles *= sparc_config.cs_period;
181 return clocksource_register_hz(&timer_cs, sparc_config.clock_rate);
189 sparc_config.load_profile_irq(cpu, 0);
197 sparc_config.load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ);
207 sparc_config
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H A Dirq.h57 struct sparc_config { struct
77 extern struct sparc_config sparc_config;
H A Dsun4m_irq.c389 sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */
390 sparc_config.features |= FEAT_L14_ONESHOT;
392 sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */
393 sparc_config.features |= FEAT_L10_CLOCKEVENT;
395 sparc_config.features |= FEAT_L10_CLOCKSOURCE;
396 sbus_writel(timer_value(sparc_config.cs_period),
470 sparc_config.init_timers = sun4m_init_timers;
471 sparc_config.build_device_irq = sun4m_build_device_irq;
472 sparc_config.clock_rate = SBUS_CLOCK_RATE;
473 sparc_config
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H A Dsun4d_irq.c462 sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */
464 sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */
465 sparc_config.features |= FEAT_L10_CLOCKEVENT;
467 sparc_config.features |= FEAT_L10_CLOCKSOURCE;
468 sbus_writel(timer_value(sparc_config.cs_period),
512 sparc_config.init_timers = sun4d_init_timers;
513 sparc_config.build_device_irq = sun4d_build_device_irq;
514 sparc_config.clock_rate = SBUS_CLOCK_RATE;
515 sparc_config.clear_clock_irq = sun4d_clear_clock_irq;
516 sparc_config
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H A Dleon_kernel.c315 sparc_config.get_cycles_offset = leon_cycles_offset;
316 sparc_config.cs_period = 1000000 / HZ;
317 sparc_config.features |= FEAT_L10_CLOCKSOURCE;
320 sparc_config.features |= FEAT_L10_CLOCKEVENT;
504 sparc_config.init_timers = leon_init_timers;
505 sparc_config.build_device_irq = _leon_build_device_irq;
506 sparc_config.clock_rate = 1000000;
507 sparc_config.clear_clock_irq = leon_clear_clock_irq;
508 sparc_config.load_profile_irq = leon_load_profile_irq;
H A Dpcic.c698 /* Coordinate with the sparc_config.clock_rate setting */
714 sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ;
715 sparc_config.features |= FEAT_L10_CLOCKEVENT;
717 sparc_config.features |= FEAT_L10_CLOCKSOURCE;
718 sparc_config.get_cycles_offset = pcic_cycles_offset;
835 sparc_config.build_device_irq = pcic_build_device_irq;
836 sparc_config.clear_clock_irq = pcic_clear_clock_irq;
837 sparc_config.load_profile_irq = pcic_load_profile_irq;
H A Dirq_32.c29 struct sparc_config sparc_config; variable in typeref:struct:sparc_config
H A Dof_device_32.c361 sparc_config.build_device_irq(op, intr[i].pri);
370 sparc_config.build_device_irq(op, irq[i]);
H A Dsun4m_smp.c256 sparc_config.load_profile_irq(cpu, 0); /* Is this needless? */

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