Searched refs:soc_mask (Results 1 - 7 of 7) sorted by relevance

/linux-master/drivers/clk/ti/
H A Dclkctrl.c524 u16 soc_mask = 0; local
542 soc_mask = CLKF_SOC_DRA72;
544 soc_mask = CLKF_SOC_DRA74;
546 soc_mask = CLKF_SOC_DRA76;
568 soc_mask |= CLKF_SOC_NONSEC;
648 (reg_data->flags & soc_mask) == 0) {
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c254 uint32_t *soc_mask)
273 if (soc_mask)
274 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
286 uint32_t mclk_mask, soc_mask; local
321 &soc_mask);
342 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
935 uint32_t sclk_mask, mclk_mask, soc_mask; local
1018 &soc_mask);
1023 renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
250 renoir_get_profiling_clk_mask(struct smu_context *smu, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) argument
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.c807 uint32_t *soc_mask)
818 if (soc_mask)
819 *soc_mask = 0;
827 if (soc_mask)
828 *soc_mask = 1;
842 if (soc_mask)
843 *soc_mask = 1;
893 uint32_t soc_mask; local
942 &soc_mask);
954 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, ma
801 vangogh_get_profiling_clk_mask(struct smu_context *smu, enum amd_dpm_forced_level level, uint32_t *vclk_mask, uint32_t *dclk_mask, uint32_t *mclk_mask, uint32_t *fclk_mask, uint32_t *soc_mask) argument
1380 uint32_t soc_mask, mclk_mask, fclk_mask; local
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c1718 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
1727 *soc_mask = 0;
1734 *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL;
1744 *soc_mask = soc_dpm_table->count - 1;
1774 uint32_t soc_mask = 0; local
1790 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
1717 vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) argument
H A Dvega20_hwmgr.c2523 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2532 *soc_mask = 0;
2539 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2549 *soc_mask = soc_dpm_table->count - 1;
2723 uint32_t sclk_mask, mclk_mask, soc_mask; local
2742 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2747 vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask);
2522 vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) argument
H A Dvega10_hwmgr.c4183 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
4192 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
4208 *soc_mask = table_info->vdd_dep_on_socclk->count - 1;
4302 uint32_t soc_mask = 0; local
4318 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4182 vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) argument
/linux-master/drivers/pinctrl/
H A Dpinctrl-single.c1402 unsigned soc_mask; local
1408 soc_mask = pcs_soc->irq_enable_mask;
1412 mask |= soc_mask;
1414 mask &= ~soc_mask;

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