Searched refs:rtw_write8_mask (Results 1 - 9 of 9) sorted by last modified time

/linux-master/drivers/net/wireless/realtek/rtw88/
H A Drtw8723d.c1095 rtw_write8_mask(rtwdev, REG_LEDCFG2, BIT(6), 0);
1096 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0);
1097 rtw_write8_mask(rtwdev, REG_GPIO_INTM + 2, BIT(4), 0);
1098 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT(1), 0);
1099 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0);
1100 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0);
1101 rtw_write8_mask(rtwdev, REG_SYS_CLKR + 1, BIT(1), 0);
1102 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT(3), 0);
H A Drtw8723x.c642 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
H A Dmain.c939 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl);
H A Dcoex.c363 rtw_write8_mask(rtwdev, addr, BIT(bitmap), data);
H A Drtw8821c.c853 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
870 rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE,
910 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
932 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
942 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
949 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA,
H A Drtw8822c.c2965 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
3019 rtw_write8_mask(rtwdev, REG_ANAPAR + 2,
3022 rtw_write8_mask(rtwdev, REG_ANAPAR + 2,
3024 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 1,
3026 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 3,
3033 rtw_write8_mask(rtwdev, REG_IGN_GNTBT4,
3040 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3042 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
3047 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3049 rtw_write8_mask(rtwde
[all...]
H A Drtw8822b.c1144 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
1185 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1187 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1189 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77);
1203 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);
1207 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1209 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1211 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66);
1214 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);
1218 rtw_write8_mask(rtwde
[all...]
H A Dbf.c134 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
182 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 0);
209 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
279 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
305 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
H A Dhci.h241 rtw_write8_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u8 data) function

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