Lines Matching refs:rtw_write8_mask
2965 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
3019 rtw_write8_mask(rtwdev, REG_ANAPAR + 2,
3022 rtw_write8_mask(rtwdev, REG_ANAPAR + 2,
3024 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 1,
3026 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 3,
3033 rtw_write8_mask(rtwdev, REG_IGN_GNTBT4,
3040 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3042 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
3047 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3049 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
3052 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3057 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3060 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
3068 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
3069 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
3070 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
3071 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
3072 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);