Searched refs:reg_entry (Results 1 - 8 of 8) sorted by relevance

/linux-master/arch/powerpc/platforms/pseries/
H A Drtas-fadump.h104 #define RTAS_FADUMP_SKIP_TO_NEXT_CPU(reg_entry) \
106 while (be64_to_cpu(reg_entry->reg_id) != \
108 reg_entry++; \
109 reg_entry++; \
H A Drtas-fadump.c283 rtas_fadump_read_regs(struct rtas_fadump_reg_entry *reg_entry, argument
288 while (be64_to_cpu(reg_entry->reg_id) != fadump_str_to_u64("CPUEND")) {
289 rtas_fadump_set_regval(regs, be64_to_cpu(reg_entry->reg_id),
290 be64_to_cpu(reg_entry->reg_value));
291 reg_entry++;
293 reg_entry++;
294 return reg_entry;
315 struct rtas_fadump_reg_entry *reg_entry; local
340 reg_entry = (struct rtas_fadump_reg_entry *)vaddr;
352 if (be64_to_cpu(reg_entry
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/linux-master/arch/powerpc/platforms/powernv/
H A Dopal-fadump.h129 struct hdat_fadump_reg_entry *reg_entry; local
136 reg_entry = (struct hdat_fadump_reg_entry *)bufp;
137 val = (cpu_endian ? be64_to_cpu(reg_entry->reg_val) :
138 (u64 __force)(reg_entry->reg_val));
140 be32_to_cpu(reg_entry->reg_type),
141 be32_to_cpu(reg_entry->reg_num),
/linux-master/drivers/gpu/drm/tegra/
H A Drgb.c32 struct reg_entry { struct
37 static const struct reg_entry rgb_enable[] = {
59 static const struct reg_entry rgb_disable[] = {
82 const struct reg_entry *table,
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c3839 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
3842 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1)
3846 &(gfx_v9_4_3_ce_reg_list[i].reg_entry),
3855 &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3869 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) {
3872 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1)
3876 &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3907 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
3910 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1)
3914 &(gfx_v9_4_3_ce_reg_list[i].reg_entry),
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H A Damdgpu_ras.h834 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
838 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
H A Damdgpu_ras.c3778 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3784 if (!reg_entry)
3788 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3789 reg_entry->seg_lo, reg_entry->reg_lo);
3792 if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
3802 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3808 if (!reg_entry)
3812 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3813 reg_entry
3777 amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev, const struct amdgpu_ras_err_status_reg_entry *reg_entry, uint32_t instance, uint32_t *memory_id) argument
3801 amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev, const struct amdgpu_ras_err_status_reg_entry *reg_entry, uint32_t instance, unsigned long *err_cnt) argument
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H A Damdgpu_gfx.h440 struct amdgpu_ras_err_status_reg_entry reg_entry; member in struct:amdgpu_gfx_ras_reg_entry

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