Searched refs:reg_bit (Results 1 - 8 of 8) sorted by relevance
/linux-master/drivers/net/ipa/ |
H A D | ipa_main.c | 234 val &= ~reg_bit(reg, PA_MASK_EN); 255 val = reg_bit(reg, CLKON_MISC); 258 val = reg_bit(reg, CLKON_GLOBAL); 259 val |= reg_bit(reg, GLOBAL_2X_CLK); 282 val &= ~reg_bit(reg, IPA_QMB_SELECT_CONS_EN); 283 val &= ~reg_bit(reg, IPA_QMB_SELECT_PROD_EN); 284 val &= ~reg_bit(reg, IPA_QMB_SELECT_GLOBAL_EN); 286 val |= reg_bit(reg, GSI_MULTI_AXI_MASTERS_DIS); 291 val |= reg_bit(reg, GSI_MULTI_INORDER_RD_DIS); 292 val |= reg_bit(re [all...] |
H A D | ipa_table.c | 364 val = reg_bit(reg, IPV6_ROUTER_HASH); 365 val |= reg_bit(reg, IPV6_FILTER_HASH); 366 val |= reg_bit(reg, IPV4_ROUTER_HASH); 367 val |= reg_bit(reg, IPV4_FILTER_HASH); 372 val = reg_bit(reg, ROUTER_CACHE); 373 val |= reg_bit(reg, FILTER_CACHE);
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H A D | reg.h | 81 static inline u32 reg_bit(const struct reg *reg, u32 field_id) function
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H A D | ipa_uc.c | 245 val = reg_bit(reg, UC_INTR);
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H A D | ipa_endpoint.c | 467 mask = reg_bit(reg, field_id); 811 val |= reg_bit(reg, HDR_OFST_PKT_SIZE_VALID); 815 val |= reg_bit(reg, HDR_OFST_METADATA_VALID); 837 val |= reg_bit(reg, HDR_ENDIANNESS); /* big endian */ 847 val |= reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID); 849 val |= reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING); 1022 val |= reg_bit(reg, SW_EOF_ACTIVE); 1133 val = enable ? reg_bit(reg, HOL_BLOCK_EN) : 0; 1278 val |= reg_bit(reg, STATUS_EN); 1644 val |= reg_bit(re [all...] |
H A D | gsi.c | 729 val |= reg_bit(reg, EV_INTYPE); 842 val |= reg_bit(reg, CHTYPE_DIR); 877 val |= reg_bit(reg, USE_DB_ENG); 885 val |= reg_bit(reg, USE_ESCAPE_BUF_ONLY); 891 val |= reg_bit(reg, DB_IN_BYTES); 1972 iowrite32(reg_bit(reg, INTYPE), gsi->virt + reg_offset(reg)); 2076 if (!(val & reg_bit(reg, ENABLED))) {
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/linux-master/drivers/perf/arm_cspmu/ |
H A D | arm_cspmu.c | 775 u32 reg_id, reg_bit, inten_off, cnten_off; local 778 reg_bit = COUNTER_TO_SET_CLR_BIT(idx); 783 writel(BIT(reg_bit), cspmu->base0 + inten_off); 784 writel(BIT(reg_bit), cspmu->base0 + cnten_off); 789 u32 reg_id, reg_bit, inten_off, cnten_off; local 792 reg_bit = COUNTER_TO_SET_CLR_BIT(idx); 797 writel(BIT(reg_bit), cspmu->base0 + cnten_off); 798 writel(BIT(reg_bit), cspmu->base0 + inten_off);
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/linux-master/drivers/net/ethernet/hisilicon/hns3/hns3pf/ |
H A D | hclge_main.c | 3768 u32 val, reg, reg_bit; local 3774 reg_bit = HCLGE_IMP_RESET_BIT; 3778 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3782 reg_bit = HCLGE_FUN_RST_ING_B; 3792 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
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