Searched refs:regUVD_VCPU_NONCACHE_SIZE0 (Results 1 - 9 of 9) sorted by last modified time

/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c376 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
485 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
H A Dvcn_v5_0_0.c337 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
441 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
H A Dvcn_v4_0_3.c392 VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0,
500 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0),
973 regUVD_VCPU_NONCACHE_SIZE0),
H A Dvcn_v4_0.c429 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
532 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
1391 regUVD_VCPU_NONCACHE_SIZE0),
/linux-master/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_5_0_0_offset.h406 #define regUVD_VCPU_NONCACHE_SIZE0 0x01d3 macro
H A Dvcn_4_0_5_offset.h399 #define regUVD_VCPU_NONCACHE_SIZE0 0x0193 macro
H A Dvcn_4_0_0_offset.h416 #define regUVD_VCPU_NONCACHE_SIZE0 0x0193 macro
H A Dvcn_4_0_3_offset.h418 #define regUVD_VCPU_NONCACHE_SIZE0 0x0193 macro
H A Dvcn_2_6_0_offset.h68 #define regUVD_VCPU_NONCACHE_SIZE0 0x0153 macro

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