Searched refs:regGCVM_CONTEXT0_CNTL (Results 1 - 8 of 8) sorted by last modified time
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | imu_v11_0.c | 214 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0xe0000000), 225 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000001, 0xe0000000), 292 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0xe0000000), 308 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000001, 0xe0000000),
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H A D | gfxhub_v3_0_3.c | 264 tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL); 269 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp); 381 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL, 468 SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL); 474 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL;
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H A D | gfxhub_v3_0.c | 259 tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL); 264 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp); 388 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL, 480 SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL); 486 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL;
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H A D | gfxhub_v11_5_0.c | 262 tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL); 267 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp); 391 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL, 483 SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL); 489 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL;
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H A D | imu_v11_0_3.c | 76 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0xe0000000), 87 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000001, 0xe0000000),
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/ |
H A D | gc_11_0_0_offset.h | 2850 #define regGCVM_CONTEXT0_CNTL 0x1688 macro [all...] |
H A D | gc_11_5_0_offset.h | 2015 #define regGCVM_CONTEXT0_CNTL 0x168c macro [all...] |
H A D | gc_11_0_3_offset.h | 3024 #define regGCVM_CONTEXT0_CNTL 0x1698 macro [all...] |
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