Searched refs:regCP_MEC_ME1_UCODE_ADDR (Results 1 - 7 of 7) sorted by path

/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c3446 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0);
3452 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
H A Dgfx_v9_4_3.c1496 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR);
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h9696 #define regCP_MEC_ME1_UCODE_ADDR 0x581a macro
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H A Dgc_11_0_3_offset.h10248 #define regCP_MEC_ME1_UCODE_ADDR macro
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H A Dgc_11_5_0_offset.h8377 #define regCP_MEC_ME1_UCODE_ADDR 0x581a macro
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H A Dgc_9_4_2_offset.h3422 #define regCP_MEC_ME1_UCODE_ADDR 0x581a macro
H A Dgc_9_4_3_offset.h7100 #define regCP_MEC_ME1_UCODE_ADDR 0x581a macro

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