Searched refs:regCP_ME1_PIPE3_INT_CNTL (Results 1 - 7 of 7) sorted by last modified time

/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c2798 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);
H A Dgfx_v11_0.c5868 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h4238 #define regCP_ME1_PIPE3_INT_CNTL 0x1e28 macro
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H A Dgc_11_5_0_offset.h3211 #define regCP_ME1_PIPE3_INT_CNTL 0x1e28 macro
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H A Dgc_9_4_3_offset.h2946 #define regCP_ME1_PIPE3_INT_CNTL 0x1088 macro
H A Dgc_11_0_3_offset.h4458 #define regCP_ME1_PIPE3_INT_CNTL 0x1e28 macro
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H A Dgc_9_4_2_offset.h485 #define regCP_ME1_PIPE3_INT_CNTL 0x1088 macro

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