Searched refs:regCP_HQD_PQ_DOORBELL_CONTROL (Results 1 - 10 of 10) sorted by path
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_amdkfd_gc_9_4_3.c | 309 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data);
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H A D | amdgpu_amdkfd_gfx_v11.c | 205 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), data);
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H A D | gfx_v11_0.c | 3789 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3854 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3916 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3977 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
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H A D | gfx_v9_4_3.c | 1574 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1688 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1757 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1813 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1814 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);
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H A D | mes_v11_0.c | 905 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 908 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 939 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1200 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1205 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1207 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/ |
H A D | gc_11_0_0_offset.h | 4630 #define regCP_HQD_PQ_DOORBELL_CONTROL 0x1fb8 macro [all...] |
H A D | gc_11_0_3_offset.h | 4854 #define regCP_HQD_PQ_DOORBELL_CONTROL 0x1fb8 macro [all...] |
H A D | gc_11_5_0_offset.h | 3603 #define regCP_HQD_PQ_DOORBELL_CONTROL 0x1fb8 macro [all...] |
H A D | gc_9_4_2_offset.h | 723 #define regCP_HQD_PQ_DOORBELL_CONTROL 0x1254 macro
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H A D | gc_9_4_3_offset.h | 3312 #define regCP_HQD_PQ_DOORBELL_CONTROL 0x1254 macro
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