Searched refs:regCP_HQD_DEQUEUE_REQUEST (Results 1 - 9 of 9) sorted by path

/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v11.c515 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_DEQUEUE_REQUEST), type);
H A Dgfx_v11_0.c3921 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
3927 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
4515 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
H A Dgfx_v9_4_3.c1693 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
1699 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,
1791 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
1806 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,
H A Dmes_v11_0.c1193 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h4646 #define regCP_HQD_DEQUEUE_REQUEST 0x1fc1 macro
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H A Dgc_11_0_3_offset.h4870 #define regCP_HQD_DEQUEUE_REQUEST 0x1fc1 macro
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H A Dgc_11_5_0_offset.h3619 #define regCP_HQD_DEQUEUE_REQUEST 0x1fc1 macro
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H A Dgc_9_4_2_offset.h739 #define regCP_HQD_DEQUEUE_REQUEST 0x125d macro
H A Dgc_9_4_3_offset.h3328 #define regCP_HQD_DEQUEUE_REQUEST 0x125d macro

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