Searched refs:refclk_mhz (Results 1 - 25 of 30) sorted by relevance

12

/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_hubbub.c56 unsigned int refclk_mhz,
62 if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
65 if (hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
69 DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
53 hubbub201_program_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hubbub.c154 uint32_t refclk_mhz,
158 ret_val = wm_ns * refclk_mhz;
171 unsigned int refclk_mhz,
183 refclk_mhz, 0x3fff);
217 refclk_mhz, 0x3fff);
227 refclk_mhz, 0x3fff);
261 refclk_mhz, 0x3fff);
271 refclk_mhz, 0x3fff);
305 refclk_mhz, 0x3fff);
315 refclk_mhz,
152 convert_and_clamp( uint32_t wm_ns, uint32_t refclk_mhz, uint32_t clamp_value) argument
168 hubbub32_program_urgent_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
358 hubbub32_program_stutter_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
504 hubbub32_program_pstate_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
657 hubbub32_program_usr_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
751 hubbub32_program_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
940 uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; local
[all...]
H A Ddcn32_hubbub.h122 unsigned int refclk_mhz,
128 unsigned int refclk_mhz,
134 unsigned int refclk_mhz,
140 unsigned int refclk_mhz,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hubbub.c220 uint32_t refclk_mhz,
224 ret_val = wm_ns * refclk_mhz;
246 unsigned int refclk_mhz,
258 refclk_mhz, 0x1fffff);
271 refclk_mhz, 0x1fffff);
283 refclk_mhz, 0x1fffff);
296 refclk_mhz, 0x1fffff);
308 refclk_mhz, 0x1fffff);
321 refclk_mhz, 0x1fffff);
333 refclk_mhz,
218 convert_and_clamp( uint32_t wm_ns, uint32_t refclk_mhz, uint32_t clamp_value) argument
243 hubbub1_program_urgent_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
357 hubbub1_program_stutter_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
502 hubbub1_program_pstate_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
583 hubbub1_program_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
[all...]
H A Ddcn10_hubbub.h427 unsigned int refclk_mhz,
450 unsigned int refclk_mhz,
455 unsigned int refclk_mhz,
460 unsigned int refclk_mhz,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_hubbub.c54 uint32_t refclk_mhz,
58 ret_val = wm_ns * refclk_mhz;
144 unsigned int refclk_mhz,
156 refclk_mhz, 0x1fffff);
191 refclk_mhz, 0x1fffff);
201 refclk_mhz, 0x1fffff);
236 refclk_mhz, 0x1fffff);
246 refclk_mhz, 0x1fffff);
281 refclk_mhz, 0x1fffff);
291 refclk_mhz,
52 convert_and_clamp( uint32_t wm_ns, uint32_t refclk_mhz, uint32_t clamp_value) argument
141 hubbub21_program_urgent_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
335 hubbub21_program_stutter_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
488 hubbub21_program_pstate_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
574 hubbub21_program_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
[all...]
H A Ddcn21_hubbub.h131 unsigned int refclk_mhz,
136 unsigned int refclk_mhz,
141 unsigned int refclk_mhz,
146 unsigned int refclk_mhz,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hubbub.c157 uint32_t refclk_mhz,
161 ret_val = wm_ns * refclk_mhz;
176 unsigned int refclk_mhz,
188 refclk_mhz, 0x3fff);
222 refclk_mhz, 0x3fff);
232 refclk_mhz, 0x3fff);
266 refclk_mhz, 0x3fff);
276 refclk_mhz, 0x3fff);
310 refclk_mhz, 0x3fff);
320 refclk_mhz,
155 convert_and_clamp( uint32_t wm_ns, uint32_t refclk_mhz, uint32_t clamp_value) argument
173 hubbub31_program_urgent_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
363 hubbub31_program_stutter_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
636 hubbub31_program_pstate_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
718 hubbub31_program_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_hubbub.c97 uint32_t refclk_mhz,
102 ret_val = wm_ns * refclk_mhz;
115 unsigned int refclk_mhz,
129 refclk_mhz, 0xfffff);
145 refclk_mhz, 0xfffff);
163 refclk_mhz, 0xfffff);
179 refclk_mhz, 0xfffff);
196 refclk_mhz, 0xfffff);
212 refclk_mhz, 0xfffff);
229 refclk_mhz,
95 convert_and_clamp( uint32_t wm_ns, uint32_t refclk_mhz, uint32_t clamp_value) argument
112 hubbub35_program_stutter_z8_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
298 hubbub35_program_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hubbub.c51 uint32_t refclk_mhz,
55 ret_val = wm_ns * refclk_mhz;
99 unsigned int refclk_mhz,
105 if (hubbub21_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
108 if (hubbub21_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
111 if (hubbub21_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
128 DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
378 uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; local
380 refclk_mhz, 0x1fffff);
49 convert_and_clamp( uint32_t wm_ns, uint32_t refclk_mhz, uint32_t clamp_value) argument
96 hubbub3_program_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
H A Ddcn30_hubbub.h128 unsigned int refclk_mhz,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubbub.c574 unsigned int refclk_mhz,
583 if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
586 if (hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
598 hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
601 DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
571 hubbub2_program_watermarks( struct hubbub *hubbub, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) argument
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddchubbub.h164 unsigned int refclk_mhz,
/linux-master/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_lib.c279 dml_print("DML PARAMS: refclk_mhz = %3.2f\n", clks_cfg->refclk_mhz);
H A Ddisplay_mode_structs.h550 double refclk_mhz; member in struct:_vcs_dpi_display_clocks_and_cfg_st
H A Ddml1_display_rq_dlg_calc.c1018 double refclk_freq_in_mhz = e2e_pipe_param->clks_cfg.refclk_mhz;
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml_display_rq_dlg_calc.c217 dml_float_t refclk_freq_in_mhz = (hw->DLGRefClkFreqMHz > 0) ? (dml_float_t) hw->DLGRefClkFreqMHz : mode_lib->soc.refclk_mhz;
274 dml_print("DML_DLG: %s: soc.refclk_mhz = %3.2f\n", __func__, mode_lib->soc.refclk_mhz);
H A Ddisplay_mode_util.c655 dml_print("DML: soc_bbox: refclk_mhz = %f\n", soc->refclk_mhz);
H A Ddml2_translation_helper.c186 out->refclk_mhz = dml2->config.bbox_overrides.dchub_refclk_mhz;
536 out->refclk_mhz = 50; // As per hardcoded reference.
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.c236 double refclk_freq_in_mhz = clks->refclk_mhz;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c362 wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_pipe] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c861 double refclk_freq_in_mhz = clks->refclk_mhz;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20v2.c815 double refclk_freq_in_mhz = clks->refclk_mhz;
H A Ddisplay_rq_dlg_calc_20.c815 double refclk_freq_in_mhz = clks->refclk_mhz;
H A Ddcn20_fpu.c1364 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1740 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2251 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;

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